Patents by Inventor Chu-Yin Hung

Chu-Yin Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12087612
    Abstract: A micro device structure including a device and a fixed structure is provided. The device has an upper surface, a lower surface, and a first side surface. The lower surface is opposite to the upper surface. The first side surface connects the upper surface and the lower surface. The fixing structure includes a connecting portion and a first turning portion. The connecting portion extends at least from the upper surface of the device to the first side surface. The first turning portion is in contact to be connected with a first end of the connecting portion and extends outward from the first side surface to be away from the first side surface. The first end of the connecting portion is located on the first side surface between the upper surface and the lower surface. A display apparatus is also provided.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: September 10, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Hsien Wu, Wei-Hung Kuo, Chu-Li Chao, Chu-Yin Hung, Yu-Hsiang Chang
  • Publication number: 20220367230
    Abstract: A micro device structure including a device and a fixed structure is provided. The device has an upper surface, a lower surface, and a first side surface. The lower surface is opposite to the upper surface. The first side surface connects the upper surface and the lower surface. The fixing structure includes a connecting portion and a first turning portion. The connecting portion extends at least from the upper surface of the device to the first side surface. The first turning portion is in contact to be connected with a first end of the connecting portion and extends outward from the first side surface to be away from the first side surface. The first end of the connecting portion is located on the first side surface between the upper surface and the lower surface. A display apparatus is also provided.
    Type: Application
    Filed: September 22, 2021
    Publication date: November 17, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Hsien Wu, Wei-Hung Kuo, Chu-Li Chao, Chu-Yin Hung, Yu-Hsiang Chang
  • Patent number: 9553176
    Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: January 24, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Jing-Yi Yan, Chih-Chieh Hsu, Hsiao-Chiang Yao, Chu-Yin Hung
  • Publication number: 20150380530
    Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.
    Type: Application
    Filed: September 9, 2015
    Publication date: December 31, 2015
    Inventors: Jing-Yi Yan, Chih-Chieh Hsu, Hsiao-Chiang Yao, Chu-Yin Hung
  • Patent number: 9165947
    Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: October 20, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Jing-Yi Yan, Chih-Chieh Hsu, Hsiao-Chiang Yao, Chu-Yin Hung
  • Patent number: 8928046
    Abstract: A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: January 6, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Jing-Yi Yan, Chu-Yin Hung, Hsiao-Chiang Yao, Yen-Yu Wu, Yen-Shih Huang
  • Publication number: 20140217400
    Abstract: A semiconductor element structure and a manufacturing method for the same are provided. The semiconductor element structure may comprise a gate electrode, a dielectric layer, an active layer, a source, a drain and a protective layer. The active layer and the gate electrode are disposed on opposing sides of the dielectric layer. The source is disposed on the active layer. The drain is disposed on the active layer. The protective layer is disposed on the active layer. The protective layer may have a hydrogen content less than or equal to 0.1 at % and a sheet resistance higher than or equal to 10? 10 Ohm/sq.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 7, 2014
    Applicant: Industrial Technology Research Institute
    Inventors: Jing-Yi YAN, Chu-Yin HUNG, Liang-Hsiang CHEN, Hsiao-Chiang YAO, Wu-Wei TSAI
  • Publication number: 20130140635
    Abstract: A semiconductor device includes a gate, a first electrode, a first insulating layer, an active layer, an etching stop layer, a second insulating layer, a source, a drain and a second electrode. The first insulating layer covers the gate and the first electrode. The active layer and the etching stop layer are disposed on the first insulating layer above the gate and the first electrode respectively. The second insulating layer covers the active layer and the etching stop layer and has a first opening and a second opening exposing the active layer and a third opening exposing the etching stop layer. The source and the drain are disposed on the second insulating layer and contact with the active layer through the first opening and the second opening respectively. The second electrode is located on the second insulating layer and contacts with the etching stop layer through the third opening.
    Type: Application
    Filed: March 23, 2012
    Publication date: June 6, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jing-Yi Yan, Chih-Chieh Hsu, Hsiao-Chiang Yao, Chu-Yin Hung
  • Publication number: 20110254061
    Abstract: A transistor including a gate, an active stacked structure, a dielectric layer, a source and a drain. The gate is located over a first surface of the dielectric layer. The active stacked structure, including a first active layer and a second active layer, is located over a second surface of the dielectric layer. The source and the drain are located over the second surface of the dielectric layer and at two sides of the active stacked structure and extend between the first active layer and the second active layer of the active stacked structure.
    Type: Application
    Filed: October 13, 2010
    Publication date: October 20, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jing-Yi Yan, Chu-Yin Hung, Hsiao-Chiang Yao, Yen-Yu Wu, Yen-Shih Huang