Patents by Inventor Chu-Yun Fu

Chu-Yun Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10269616
    Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen
  • Publication number: 20170330791
    Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
    Type: Application
    Filed: June 5, 2017
    Publication date: November 16, 2017
    Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen
  • Patent number: 9716091
    Abstract: A fin field effect transistor (FinFET) including a first insulation region and a second insulation region and fin there between. A gate stack is disposed over a first portion of the fin. A strained source/drain material is disposed over a second portion of the fin. The strained source/drain material has a flat top surface extending over the first and second insulation regions. The first insulation region may include a tapered top surface.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: July 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chu-Yun Fu, Hung-Ming Chen, Shu-Tine Yang, Shin-Yeh Huang
  • Patent number: 9673082
    Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen
  • Publication number: 20160379977
    Abstract: A fin field effect transistor (FinFET) including a first insulation region and a second insulation region and fin there between. A gate stack is disposed over a first portion of the fin. A strained source/drain material is disposed over a second portion of the fin. The strained source/drain material has a flat top surface extending over the first and second insulation regions. The first insulation region may include a tapered top surface.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 29, 2016
    Inventors: Hung-Ta LIN, Chu-Yun FU, Hung-Ming CHEN, Shu-Tine YANG, Shin-Yeh HUANG
  • Patent number: 9379215
    Abstract: A method of fabricating a fin field effect transistor (FinFET) including forming a first insulation region and a second insulation region and fin there between. The method further includes forming a gate stack over a portion of the fin and over a portion of the first and second insulation regions. The method further includes tapering the top surfaces of the first and second insulation regions not covered by the gate stack.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chu-Yun Fu, Hung-Ming Chen, Shu-Tine Yang, Shin-Yeh Huang
  • Publication number: 20160133506
    Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
    Type: Application
    Filed: December 28, 2015
    Publication date: May 12, 2016
    Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen
  • Publication number: 20160087079
    Abstract: A method of fabricating a fin field effect transistor (FinFET) including forming a first insulation region and a second insulation region and fin there between. The method further includes forming a gate stack over a portion of the fin and over a portion of the first and second insulation regions. The method further includes tapering the top surfaces of the first and second insulation regions not covered by the gate stack.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 24, 2016
    Inventors: Hung-Ta Lin, Chu-Yun Fu, Hung-Ming Chen, Shu-Tine Yang, Shin-Yeh Huang
  • Patent number: 9224606
    Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen
  • Patent number: 9209300
    Abstract: A fin field effect transistor including a first insulation region and a second insulation region over a top surface of a substrate. The first insulation region includes tapered top surfaces, and the second insulation region includes tapered top surfaces. The fin field effect transistor further includes a fin extending above the top surface between the first insulation region and the second insulation region. The fin includes a first portion having a top surface below the tapered top surfaces of the first insulation region. The fin includes a second portion having a top surface above the tapered top surfaces of the first insulation region.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chu-Yun Fu, Shin-Yeh Huang, Shu-Tine Yang, Hung-Ming Chen
  • Patent number: 8883597
    Abstract: The present disclosure provides a method of fabricating a FinFET element including providing a substrate including a first fin and a second fin. A first layer is formed on the first fin. The first layer comprises a dopant of a first type. A dopant of a second type is provided to the second fin. High temperature processing of the substrate is performed on the substrate including the formed first layer and the dopant of the second type.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hung Chang, Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Yu-Rang Hsu, Ding-Yuan Chen
  • Publication number: 20140327091
    Abstract: A fin field effect transistor including a first insulation region and a second insulation region over a top surface of a substrate. The first insulation region includes tapered top surfaces, and the second insulation region includes tapered top surfaces. The fin field effect transistor further includes a fin extending above the top surface between the first insulation region and the second insulation region. The fin includes a first portion having a top surface below the tapered top surfaces of the first insulation region. The fin includes a second portion having a top surface above the tapered top surfaces of the first insulation region.
    Type: Application
    Filed: July 22, 2014
    Publication date: November 6, 2014
    Inventors: Hung-Ta LIN, Chu-Yun FU, Shin-Yeh HUANG, Shu-Tine YANG, Hung-Ming CHEN
  • Patent number: 8822293
    Abstract: A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate, wherein the semiconductor substrate and a sidewall of the gate dielectric has a joint point; forming a gate electrode over the gate dielectric; forming a mask layer over the semiconductor substrate and the gate electrode, wherein a first portion of the mask layer adjacent the joint point is at least thinner than a second portion of the mask layer away from the joint point; after the step of forming the mask layer, performing a halo/pocket implantation to introduce a halo/pocket impurity into the semiconductor substrate; and removing the mask layer after the halo/pocket implantation.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: September 2, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Yihang Chiu, Shu-Tine Yang, Jyh-Cherng Sheu, Chu-Yun Fu, Cheng-Tung Lin
  • Patent number: 8809940
    Abstract: A FinFET is described, the FinFET includes a substrate including a top surface and a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces. The FinFET further includes a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin includes a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin includes a non-recessed portion having a top surface higher than the tapered top surfaces. The FinFET further includes a gate stack over the non-recessed portion of the fin.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chu-Yun Fu, Shin-Yeh Huang, Shu-Tine Yang, Hung-Ming Chen
  • Patent number: 8580653
    Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
  • Publication number: 20130171803
    Abstract: A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide.
    Type: Application
    Filed: February 25, 2013
    Publication date: July 4, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tze-Liang LEE, Pei-Ren JENG, Chu-Yun FU, Chyi Shyuan CHERN, Jui-Hei HUANG, Chih-Tang PENG, Hao-Ming LIEN
  • Patent number: 8440517
    Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: May 14, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Ta Lin, Chu-Yun Fu, Shin-Yeh Huang, Shu-Tine Yang, Hung-Ming Chen
  • Patent number: 8404561
    Abstract: The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: March 26, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tze-Liang Lee, Pei-Ren Jeng, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng, Hao-Ming Lien
  • Patent number: 8173503
    Abstract: A method of forming an integrated circuit device includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and performing a pre-amorphized implantation (PAI) by implanting a first element selected from a group consisting essentially of indium and antimony to a top portion of the semiconductor substrate adjacent to the gate structure. The method further includes, after the step of performing the PAI, implanting a second element different from the first element into the top portion of the semiconductor substrate. The second element includes a p-type element when the first element includes indium, and includes an n-type element when the first element includes antimony.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: May 8, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yihang Chiu, Chu-Yun Fu
  • Publication number: 20120094464
    Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.
    Type: Application
    Filed: December 23, 2011
    Publication date: April 19, 2012
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chen-Nan Yeh, Chu-Yun Fu, Ding-Yuan Chen