Patents by Inventor Chu-Yung Liu

Chu-Yung Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200243121
    Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: selecting a programmed word line, where the programmed word line has a plurality of segments respectively corresponding to a plurality of bit lines; providing a program voltage to a voltage receiving end of the programmed word line, and sequentially transmitting the program voltage to the segments; respectively providing a plurality of bit line voltages to the bit lines at a plurality of enable time points and turning on a string selection switch at a setting time point; and setting voltage values of the bit line voltages according to the segments corresponding to the bit lines, respectively, or setting the enable time points according to the segments corresponding to the bit lines, or setting the setting time point according to a voltage transmission delay of the programmed word line.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chu-Yung Liu, Hsing-Wen Chang, Yung-Hsiang Chen, Yao-Wen Chang
  • Publication number: 20190067246
    Abstract: A semiconductor structure includes a substrate, a stack of alternate conductive layers and insulating layers, a hole, and an active structure. The stack is disposed on the substrate. The conductive layers include an ith conductive layer and a jth conductive layer disposed above the ith conductive layer, the ith conductive layer has a thickness ti, the jth conductive layer has a thickness tj, and tj is larger than ti. The hole penetrates through the stack. The hole has a diameter Di and a diameter Dj corresponding to the ith conductive layer and the jth conductive layer, respectively, and Dj is larger than Di. The active structure is disposed in the hole. The active structure includes a channel layer. The channel layer is disposed along a sidewall of the hole and isolated from the conductive layers of the stack.
    Type: Application
    Filed: August 23, 2017
    Publication date: February 28, 2019
    Inventors: Guan-Wei Wu, Chu-Yung Liu, Yao-Wen Chang, I-Chen Yang
  • Publication number: 20180158950
    Abstract: A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.
    Type: Application
    Filed: December 7, 2016
    Publication date: June 7, 2018
    Inventors: Yung-Hsiang Chen, Yao-Wen Chang, Chu-Yung Liu, I-Chen Yang, Hsin-Wen Chang
  • Patent number: 9437303
    Abstract: A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 6, 2016
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chu-Yung Liu, Hsing-Wen Chang, Yao-Wen Chang, Tao-Cheng Lu
  • Patent number: 8929134
    Abstract: A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line to a first voltage, biasing a string select transistor to a second voltage; and ramping down the string select transistor to the first voltage. In particular, the second voltage is higher than the first voltage.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: January 6, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chu Yung Liu, Hsing Wen Chang, Yao Wen Chang, Tao Cheng Lu
  • Publication number: 20140226411
    Abstract: A method of programming a NAND flash memory cell string. The method includes a pre-boost stage configured to elevate channel voltage of a selected memory cell, and a boost stage is introduced after the pre-boost stage. The pre-boost stage has at least the following steps of biasing a bit line to a first voltage, biasing a string select transistor to a second voltage; and ramping down the string select transistor to the first voltage. In particular, the second voltage is higher than the first voltage.
    Type: Application
    Filed: February 8, 2013
    Publication date: August 14, 2014
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: CHU YUNG LIU, HSING WEN CHANG, YAO WEN CHANG, TAO CHENG LU
  • Publication number: 20140126296
    Abstract: A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is an integer greater than 2. The memory array includes a plurality of memory cells and is connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. Each of the page buffers is connected to N bit lines of the bit lines, and N is an integer equal to or greater than 3. A jth page buffer drives an (N*(j?1)+1)th bit line to an (N*j)th bit line during the enabling period, and one of an (i?1)th bit line and an (i+1)th bit line is not driven when an ith bit line is not driven, wherein j is an integer and 1?j?M, and i is an integer and 1<i<M*N.
    Type: Application
    Filed: January 9, 2014
    Publication date: May 8, 2014
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Hsing-Wen Chang, Yao-Wen Chang, Chu-Yung Liu
  • Patent number: 8644081
    Abstract: A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the ith, (i+N)th, (i+2N)th, . . . , (i+(M?1)*N)th bit lines are driven by the M page buffers during the ith sub-period, so as to program the memory cells electrically connected to the specific word line, wherein i is an integer and 1?i?N.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: February 4, 2014
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hsing-Wen Chang, Yao-Wen Chang, Chu-Yung Liu
  • Publication number: 20120243334
    Abstract: A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is a positive integer. The memory array includes a plurality of memory cells and is electrically connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. The M page buffers divide the enabling period into N sub-periods, wherein N is an integer greater than 2. Furthermore, the ith, (i+N)th, (i+2N)th, . . . , (i+(M?1)*N)th bit lines are driven by the M page buffers during the ith sub-period, so as to program the memory cells electrically connected to the specific word line, wherein i is an integer and 1?i?N.
    Type: Application
    Filed: March 23, 2011
    Publication date: September 27, 2012
    Applicant: Macronix International Co., Ltd.
    Inventors: Hsing-Wen CHANG, Yao-Wen CHANG, Chu-Yung LIU
  • Publication number: 20110018049
    Abstract: The present invention relates to a charge trapping device and a method for manufacturing the same. The charge trapping device includes: a substrate having a first surface and an opposite second surface; a tunneling insulating layer, disposed on the first surface of the substrate; a charge trapping layer, disposed on the tunneling insulating layer and including a first dielectric layer and a second dielectric layer, in which the first dielectric layer is connected to the tunneling insulating layer, the second dielectric layer is disposed over the first dielectric layer, and a conduction band offset between the first dielectric layer and the substrate is larger than that between the second dielectric layer and the substrate; and a blocking insulating layer, disposed on the charge trapping layer and connected to the second dielectric layer. Accordingly, the charge trapping device of the present invention has excellent programming, and erasing and charge retention properties.
    Type: Application
    Filed: December 1, 2009
    Publication date: January 27, 2011
    Applicant: National Tsing Hua University
    Inventors: Kuei-Shu Chang-Liao, Pei-Jer Tzeng, Chu-Yung Liu, Zong-Hao Ye, Ping-Hung Tsai, Te-Chiang Liu