Patents by Inventor Chua Chee Tee

Chua Chee Tee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming a high K metallic dielectric layer
    Patent number: 6764914
    Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: July 20, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Alex See, Cher Liang Randall Cha, Shyue Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong, Jun Song, Chua Chee Tee
  • Method of forming a high K metallic dielectric layer
    Publication number: 20030104673
    Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures.
    Type: Application
    Filed: November 7, 2002
    Publication date: June 5, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Alex See, Cher Liang Randall Cha, Shyue Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong, Jun Song, Chua Chee Tee
  • Method of forming of high K metallic dielectric layer
    Patent number: 6492242
    Abstract: A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures.
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: December 10, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Alex See, Cher Liang Randall Cha, Shyuz Fong Quek, Ting Cheong Ang, Wye Boon Loh, Sang Yee Loong, Jun Song, Chua Chee Tee
  • Method to fabricate RF inductors with minimum area
    Patent number: 6387747
    Abstract: A method for forming an RF inductor of helical shape having high Q and minimum area. The inductor is fabricated of metal or damascened linear segments formed on three levels of intermetal dielectric layers and interconnected by metal filled vias to form the complete helical shape with electrical continuity.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: May 14, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Randall Cha, Tae Jong Lee, Alex See, Lap Chan, Chua Chee Tee
  • Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors
    Patent number: 6284590
    Abstract: A method for fabricating a metal-insulator-metal capacitor wherein top metal corner shaping during patterning is eliminated is described. An insulating layer is provided overlying a semiconductor substrate. A first metal layer is deposited over the insulating layer. A capacitor dielectric layer is deposited overlying the first metal layer. A second metal layer is deposited overlying the capacitor dielectric layer and patterned to form a top metal electrode. A flowable material layer is deposited overlying the capacitor dielectric and the top metal electrode and anisotropically etched away to leave spacers on sidewalls of the top metal electrode. A photoresist mask is formed overlying the capacitor dielectric and the top metal electrode wherein the spacers provide extra photoresist thickness at the sidewalls of the top metal layer.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: September 4, 2001
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Randall Cher Liang Cha, Cheng Yeow Ng, Shao-Fu Sanford Chu, Tae Jong Lee, Chua Chee Tee