Patents by Inventor Chuan C. Chang

Chuan C. Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4623912
    Abstract: A semiconductor integrated circuit includes a nitrided silicon dioxide layer typically 50 to 400 Angstroms thick located on a semiconductor medium. The nitrided layer is an original silicon dioxide layer that has been nitrided at its top surface, as by rapid (flash) heating in ammonia to about 1250 degrees C., in such a way that the resulting nitrided silicon dioxide layer is essentially a compound layer of silicon nitroxide on silicon dioxide in which the atomic concentration fraction of nitrogen falls from a value greater than 0.13 at the top surface of the compound layer to a value of about 0.13 within 30 Angstroms or less beneath the top surface, and advantageously to values of less than about 0.05 everywhere at distances greater than about 60 Angstroms or less beneath the top surface, except that the nitrogen fraction can rise to as much as about 0.10 in the layer at distances within about 20 Angstroms from the interface of the nitrided layer and the underlying semiconductor medium.
    Type: Grant
    Filed: December 5, 1984
    Date of Patent: November 18, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Chuan C. Chang, Dawon Kahng, Avid Kamgar, Louis C. Parrillo
  • Patent number: 4324038
    Abstract: A method for making a MOSFET device (20) in a semiconductor body (10) includes the step of forming source and drain contact electrodes (12.1, 12.2) prior to growth of the gate oxide (10.3) and after formation of a high conductivity surface region (10.5). The exposed mutually opposing sidewall edges of each of the contact electrodes (12.1, 12.2) are coated with a sidewall silicon dioxide layer (15.1, 15.2), and the then exposed surface of the semiconductor body (10) between these sidewalls is etched to depth beneath the high conductivity surface region (10.5) in order to separate it into the source and drain regions (10.1, 10.2).Formation of the high conductivity region may be omitted by using Schottky barrier or impurity doped material for the contact electrodes (12.1, 12.2).
    Type: Grant
    Filed: November 24, 1980
    Date of Patent: April 13, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Chuan C. Chang, James A. Cooper, Jr., Dawon Kahng, Shyam P. Murarka
  • Patent number: 4314855
    Abstract: Contaminants that accumulate on test probes utilized to contact aluminum pads on integrated circuit chips cause the probe resistance to become unacceptably high. As disclosed herein, the contaminants (predominantly a mixture of aluminum and aluminum oxide) are substantially removed by immersing the probes in boiling water. Adding small quantities of phosphoric and/or hydrofluoric acids to the water further improves the cleaning action.
    Type: Grant
    Filed: December 17, 1979
    Date of Patent: February 9, 1982
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Chuan C. Chang, Jitendra Kumar
  • Patent number: 4179534
    Abstract: A semiconductor device with a low resistance ohmic contact, strongly adherent to the n-type surface of a body (11) of Group III-V compound semiconductor is obtained by a process including the sequential deposition of gold (13), tin (14) and gold (15) at a surface temperature of less than 200 degrees C followed by a heat treatment in a nonoxidizing atmosphere. This process has shown particular advantage when applied to aluminum containing compound semiconductors (e.g., gallium aluminum arsenide). For such use an initial deposition of aluminum (16) has proven particularly successful in producing consistently low resistance ohmic contacts. The invention has been used in the production of light emitting diodes.
    Type: Grant
    Filed: May 24, 1978
    Date of Patent: December 18, 1979
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Chuan C. Chang, Felix Ermanis, Robert J. McCoy, Shohei Nakahara, Tan T. Sheng
  • Patent number: 4144634
    Abstract: A method of fabricating gallium arsenide MOS devices with improved stoichiometric and electrical properties is disclosed. The device includes a gallium arsenide substrate overlaid with a native oxide and an aluminum oxide layer. The device is fabricated using a plasma oxidizing process.
    Type: Grant
    Filed: June 28, 1977
    Date of Patent: March 20, 1979
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Chuan C. Chang, Robert P. H. Chang, James J. Coleman, Tan T. Sheng