Patents by Inventor Chuan-Chen Lee

Chuan-Chen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080024510
    Abstract: The texture engine, provided in this disclosure, comprises a texel location calculator, a texture cache unit, and a video processing unit. The texel location calculator receives a texture and video request for a pixel, including location information of texture data for the pixel in a texture map stored in a memory unit and information of video processing required for the pixel. The texel location calculator computes memory addresses of the texture data in the memory unit and graphics data required for the pixel when performing the video processing specified in the texture and video request in the memory unit. The texture cache unit retrieves a copy of the graphics data and texture data from the memory unit with the memory addresses computed by the texel location calculator. The video processing unit receives the graphics data to perform the video processing specified in the texture and video request on the graphics data.
    Type: Application
    Filed: July 27, 2006
    Publication date: January 31, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Chuan-Chen Lee, Ming-Hsuan Tan, Ko-Fang Wang
  • Patent number: 7102690
    Abstract: A method for synthesizing a clock signal with multiple frequency outputs for use in a converter for converting a non-interlacing scan data into an interlacing scan data is disclosed. The converter provides a first reference clock signal with a frequency F1. The method includes the steps of receiving the first reference clock signal with the frequency F1 to generate and output a clock signal with a frequency F1×N, proceeding a divided-by-P1 and a divided-by-P2 operations on the clock signal with a frequency F1×N, respectively, to output a first output clock signal with a frequency F1×N/P1 and a second output clock signal with a frequency F1×N/P2, respectively. The value P2/P1 correlates to a ratio of the pixel number of a horizontal scan line in the non-interlacing scan data to that in the interlacing scan data. In addition, a clock signal synthesizer with multiple frequency outputs is also disclosed.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: September 5, 2006
    Assignee: Via Technologies Inc.
    Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
  • Patent number: 7084925
    Abstract: A method for processing an image to convert a non-interlacing scan data into an interlacing scan data is disclosed. The method includes the steps of receiving a non-interlacing scan data, the non-interlacing scan data including plural pixels, replacing a color space value of a selected one of the pixels in the non-interlacing scan data with a combination of color space values of the selected one pixel and at least one adjacent pixel to obtain a blurringly filtered non-interlacing scan data, scaling the blurringly filtered non-interlacing scan data according to a specific algorithm, and converting the blurringly filtered non-interlacing scan data into an interlacing scan data. An image-processing device for converting a non-interlacing scan data into an interlacing scan data is also disclosed. The device includes a blurring filter, a scaler and a converter.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: August 1, 2006
    Assignee: VIA Technologies, Inc.
    Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
  • Patent number: 7061537
    Abstract: An adaptive deflicker method for use in converting a non-interlacing scan data into an interlacing scan data is disclosed. The method includes the steps of receiving a non-interlacing scan data, wherein the non-interlacing scan data includes plural scan lines, proceeding a deflicker operation on an edge line of the non-interlacing scan data, exempting a non-edge line of the non-interlacing scan data from the deflicker operation, and converting the non-interlacing scan data into an interlacing scan data. In addition, an adaptive deflicker filter for use in converting a non-interlacing scan data into an interlacing scan data is also disclosed. The adaptive deflicker filter includes an edge-line detector and a deflicker filter.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: June 13, 2006
    Assignee: Via Technologies, Inc.
    Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
  • Patent number: 7002634
    Abstract: A clock generating apparatus is provided for producing an output clock signal responsive to a source clock signal with a source frequency and a reference clock signal with a reference frequency. The clock generating apparatus includes a counting sequence generator, a measuring value generator and a ratio counter. The counting sequence generator is used for outputting a series of counting values in response to a triggering signal with a specified period determined by the source frequency of the source clock signal and a predetermined counting value. The measuring value generator generates a measuring value by operating the series of counting values according to a predetermined formula. The ratio counter produces the output clock signal with a frequency determined by the source frequency of the source clock signal and the measuring value.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: February 21, 2006
    Assignee: Via Technologies, Inc.
    Inventors: Chia-Liang Tai, Yi-Chieh Huang, Chuan-Chen Lee
  • Publication number: 20030174245
    Abstract: A method for synthesizing a clock signal with multiple frequency outputs for use in a converter for converting a non-interlacing scan data into an interlacing scan data is disclosed. The converter provides a first reference clock signal with a frequency F1. The method includes the steps of receiving the first reference clock signal with the frequency F1 to generate and output a clock signal with a frequency F1×N, proceeding a divided-by-P1 and a divided-by-P2 operations on the clock signal with a frequency F1×N, respectively, to output a first output clock signal with a frequency F1×N/P1 and a second output clock signal with a frequency F1×N/P2, respectively. The value P2/P1 correlates to a ratio of the pixel number of a horizontal scan line in the non-interlacing scan data to that in the interlacing scan data. In addition, a clock signal synthesizer with multiple frequency outputs is also disclosed.
    Type: Application
    Filed: August 30, 2002
    Publication date: September 18, 2003
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
  • Publication number: 20030174247
    Abstract: An adaptive deflicker method for use in converting a non-interlacing scan data into an interlacing scan data is disclosed. The method includes the steps of receiving a non-interlacing scan data, wherein the non-interlacing scan data includes plural scan lines, proceeding a deflicker operation on an edge line of the non-interlacing scan data, exempting a non-edge line of the non-interlacing scan data from the deflicker operation, and converting the non-interlacing scan data into an interlacing scan data. In addition, an adaptive deflicker filter for use in converting a non-interlacing scan data into an interlacing scan data is also disclosed. The adaptive deflicker filter includes an edge-line detector and a deflicker filter.
    Type: Application
    Filed: November 12, 2002
    Publication date: September 18, 2003
    Applicant: VIA Technologies, Inc.
    Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
  • Publication number: 20030174246
    Abstract: A method for processing an image to convert a non-interlacing scan data into an interlacing scan data is disclosed. The method includes the steps of receiving a non-interlacing scan data, the non-interlacing scan data including plural pixels, replacing a color space value of a selected one of the pixels in the non-interlacing scan data with a combination of color space values of the selected one pixel and at least one adjacent pixel to obtain a blurringly filtered non-interlacing scan data, scaling the blurringly filtered non-interlacing scan data according to a specific algorithm, and converting the blurringly filtered non-interlacing scan data into an interlacing scan data. An image-processing device for converting a non-interlacing scan data into an interlacing scan data is also disclosed. The device includes a blurring filter, a scaler and a converter.
    Type: Application
    Filed: September 3, 2002
    Publication date: September 18, 2003
    Applicant: VIA Technologies, Inc.
    Inventors: Chuan-Chen Lee, Chia-Liang Tai, Yi-Chieh Huang
  • Publication number: 20030112371
    Abstract: A clock generating apparatus is provided for producing an output clock signal responsive to a source clock signal with a source frequency and a reference clock signal with a reference frequency. The clock generating apparatus includes a counting sequence generator, a measuring value generator and a ratio counter. The counting sequence generator is used for outputting a series of counting values in response to a triggering signal with a specified period determined by the source frequency of the source clock signal and a predetermined counting value. The measuring value generator generates a measuring value by operating the series of counting values according to a predetermined formula. The ratio counter produces the output clock signal with a frequency determined by the source frequency of the source clock signal and the measuring value.
    Type: Application
    Filed: July 16, 2002
    Publication date: June 19, 2003
    Inventors: Chia-Liang Tai, Yi-Chieh Huang, Chuan-Chen Lee