Abstract: An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.

Abstract: An operating circuit includes an amplifier having a first input terminal coupled to a reference voltage; a first transconducting element for selectively generating a first current; a second transconducting element for selectively generating a second current; a resistive element having a first terminal coupled to the first transconducting element; a capacitive element having a first terminal selectively coupled to the second transconducting element; and a switching device. The switching device has a first configuration to connect the first terminal of the capacitive element to the second transconducting element and connect the first terminal of the resistive element to a second input terminal of the amplifier, and has a second configuration to disconnect the first terminal of the capacitive element from the second transconducting element and connect the second input terminal of the amplifier to the first terminal of the capacitive element instead of the first terminal of the resistive element.

Abstract: The invention discloses a signal detection apparatus and method thereof for detecting whether an input signal of a set of serial ATA signals is an out of band (OOB) signal. The signal detection apparatus includes a calibrated clock generation device, a signal processor, and a logic determination device. The calibrated clock generation device generates a sampling clock signal according to a predetermined clock signal. The signal processor generates a plurality of detection results based on the sampling clock signal and the input signal. The logic determination device receives the plural of detection results and determines whether the input signal is the OOB signal.

Abstract: An integrated circuit includes: a substrate; and a bond pad array on the substrate. The bond pad array includes: a row of inner bond pads, each inner bond pad positioned with respect to a plurality of inner pad openings; a plurality of first inner metal layers respectively coupled to the inner bond pads for transmitting signals between the inner pads and an internal circuit, where at least one first inner metal layer has a width less than a width of a corresponding inner bond pad; a row of outer bond pads, staggered with respect to the row of inner bond pads; and a plurality of first outer metal layers respectively coupled to the outer bond pads for transmitting signals between the outer pads and the internal circuit, where at least one inner bond pad overlaps adjacent first outer metal layers.

Abstract: A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode.

Abstract: A phase-locked loop includes a processing unit, a voltage-controlled oscillator, and a control unit. The processing unit generates a control voltage to a node according to a phase difference between a reference clock and a first feedback clock. The voltage-controlled oscillator generates the first feedback clock according to a voltage of the node. The control unit deactivates the voltage-controlled oscillator and provides a start voltage to the node in a power-down mode, and activates the voltage-controlled oscillator to generate the first feedback clock according to the voltage of the node in a power-on mode. The control unit stops providing the start voltage in the power-on mode.

Abstract: A noise removal circuit. The noise removal circuit comprises a crystal oscillator and a level decision module. The crystal oscillator generates an oscillating signal and an output clock signal. The level decision module detects the signal level of the oscillating signal and outputs the output clock signal when the signal level of the oscillating signal exceeds a first reference level.

Abstract: A noise removal circuit. The noise removal circuit comprises a crystal oscillator and a level decision module. The crystal oscillator generates an oscillating signal and an output clock signal. The level decision module detects the signal level of the oscillating signal and outputs the output clock signal when the signal level of the oscillating signal exceeds a first reference level.

Abstract: A noise removal circuit. The noise removal circuit comprises a crystal oscillator and a level decision module. The crystal oscillator generates an oscillating signal and an output clock signal. The level decision module detects the signal level of the oscillating signal and outputs the output clock signal when the signal level of the oscillating signal exceeds a first reference level.

Abstract: A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.

Abstract: A signal generating system for generating a validation signal includes: a phase lock loop (PLL) for locking an output clock to a specific clock frequency; and a digital signal generation circuit. The digital signal generating circuit includes: a triggering circuit, electrically coupled to the PLL, for determining whether the output clock of the PLL is in a frequency range, and outputting a triggering signal if the output clock is in a frequency range; and a signal generating device, electrically coupled to the triggering circuit and the PLL, for generating the validation signal according to the output clock when receiving the triggering signal; wherein before the output clock is in the frequency range, the PLL continuously outputs the output clock.

Abstract: A data driver for driving multiple data lines on an LCD panel according to multiple channels of pixel data. In the data driver, a digital buffer receives and stores the pixel data at several times and selectively outputs a channel of the pixel data at a time. A DAC receives the pixel data output from the digital buffer at several times, converts the pixel data into multiple channels of analog pixel data and outputs the analog pixel data at several times. An analog buffer receives the analog pixel data output from the DAC at several times and outputs the analog pixel data at a time. An output buffer receives the analog pixel data output from the analog buffer so as to drive the data lines.

Abstract: A method for driving an LCD monitor is disclosed. The LCD monitor includes a voltage selection unit used for outputting a plurality of driving voltages according to display data, and a plurality of output buffers each electrically connected to the voltage selection circuit and a corresponding pixel. In the beginning, an output port of each output buffer approaches voltage at an input port. Then, the output ports of the driving units, which approach the same input voltage, are electrically connected to have an average voltage. In addition, the LCD monitor further includes a timing controller for controlling operation of the output buffers. When output ports of the output buffers, which approach the same input voltage, are electrically connected, the output buffers are turned off for saving power.

Abstract: A capacitor digital-to-analog converter for N-bit digital-to-analog conversion comprises a converter capacitor network comprising 2N capacitors and 2N+1 MOS switches and an output buffer. The MOS switches are connected in a series chain at their respective source/drain, and each of the capacitors has a first electrode connected to a corresponding joining node between two consecutive MOS switches in the series chain and a second electrode connected together to a common node. The output buffer comprises a differential amplifier and an output amplifier, the differential amplifier has 2N discrete inputs each connected to a corresponding one of the first electrodes of the capacitors in the converter capacitor network.

Abstract: An apparatus and a method for data signal scattering conversion. The apparatus includes a scattering multiplexer, a digital-to-analog converter, and a scattering demultiplexer. The scattering multiplexer is for receiving p digital data signals and outputting the q-th digital data signal of the p digital data signals. The digital-to-analog converter is to perform digital-to-analog conversion of the q-th digital data signal and output an analog data signal. The scattering demultiplexer has p output terminals, and is used for outputting the analog data signal through the q-th output terminal. Offset voltages output from the digital-to-analog converter are scattered over a number of data lines so that undesired points with abnormally deep or light colors due to the output offset voltages, are difficult to perceive.

Abstract: The invention discloses a signal detection apparatus and method thereof for detecting whether an input signal of a set of serial ATA signals is an out of band (OOB) signal. The signal detection apparatus includes a calibrated clock generation device, a signal processor, and a logic determination device. The calibrated clock generation device generates a sampling clock signal according to a predetermined clock signal. The signal processor generates a plurality of detection results based on the sampling clock signal and the input signal. The logic determination device receives the plural of detection results and determines whether the input signal is the OOB signal.

Abstract: An apparatus for switching output voltage signals includes a resistor string, a first switching device set for delivering a number of gamma voltage input signals, a second switching device set for delivering a high voltage input signal and a low voltage input signal, and a switch selecting device coupled to the first switching device set and the second switching device set. When the switch selecting device outputs a first signal, the first switching device set can deliver the gamma voltage input signals to the resistor string; when the switch selecting device outputs a second signal, the second switching device set will deliver the high voltage input signal and the low voltage input signal to the resistor string.

Abstract: A dynamic CMOS level shifter circuit apparatus in a digital electronic system is disclosed for shifting a signal of a first logic family at a first lower voltage level to a second higher voltage level for a second logic family. The shifter circuit apparatus comprises a first transistor pair that has a first PMOS and a first NMOS transistor connected in series; a second transistor pair that has a second PMOS and a second NMOS transistor connected in series; and a power-down control PMOS transistor. The first and second transistor pairs are connected in parallel, and the parallel connection is connected in series with the power-down control PMOS transistor across the power and ground level of the system. The node at which the drain terminals of the transistors of the first transistor pair is connected together is also connected to the gate of the second PMOS transistor.

Abstract: A layout structure of a decoder with m*n nodes and the method thereof are provided. The nodes comprise a plurality of transistor nodes and a plurality of channel nodes. The manufacturing method of the transistor node comprises forming a gate, a first source/drain region and a second source/drain region. The channel node is fabricated by forming a channel. The channel, the first source/drain region and the second source/drain region are formed at the same time with the same material. The decoder circuit with smaller width is accomplished without additional mask in the invention.

Abstract: A data driver for driving multiple data lines on an LCD panel according to multiple channels of pixel data. In the data driver, a digital buffer receives and stores the pixel data at several times and selectively outputs a channel of the pixel data at a time. A DAC receives the pixel data output from the digital buffer at several times, converts the pixel data into multiple channels of analog pixel data and outputs the analog pixel data at several times. An analog buffer receives the analog pixel data output from the DAC at several times and outputs the analog pixel data at a time. An output buffer receives the analog pixel data output from the analog buffer so as to drive the data lines.