Patents by Inventor Chuan Cheng Pan

Chuan Cheng Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11256648
    Abstract: A method for managing a pool of physical functions in a PCIe integrated endpoint includes receiving a configuration instruction indicating a topology for a PCIe connected integrated endpoint (IE), and implementing the topology on the IE. The method further includes receiving a hot plug instruction, and, based at least in part, on the hot plug instruction, adding or removing a virtual endpoint (vEP) to or from a virtual downstream port (vDSP) on the IE.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: February 22, 2022
    Assignee: XILINX, INC.
    Inventors: Chuan Cheng Pan, Hanh Hoang, Chandrasekhar S. Thyamagondlu
  • Patent number: 11196715
    Abstract: A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to process a signature of the portion and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice-aggregated cryptographic slice.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 7, 2021
    Assignee: XILINX, INC.
    Inventors: Anujan Varma, Poching Sun, Chuan Cheng Pan, Suchithra Ravi
  • Publication number: 20210021575
    Abstract: A system comprises one or more slice-aggregated cryptographic slices each configured to perform a plurality of operations on an incoming data transfer at a first processing rate by aggregating one or more individual cryptographic slices each configured to perform the plurality of operations on a portion of the incoming data transfer at a second processing rate. Each of the individual cryptographic slices comprises in a serial connection an ingress block configured to take the portion of the incoming data transfer at the second processing rate, a cryptographic engine configured to perform the operations on the portion of the incoming data transfer, an egress block configured to process a signature of the portion and output the portion of the incoming data transfer once the operations have completed. The first processing rate of each slice-aggregated cryptographic slices equals aggregated second processing rates of the individual cryptographic slices in the slice-aggregated cryptographic slice.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 21, 2021
    Inventors: Anujan VARMA, Poching SUN, Chuan Cheng PAN, Suchithra RAVI
  • Patent number: 10659437
    Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: May 19, 2020
    Assignee: Xilinx, Inc.
    Inventors: Ravi Sunkavalli, Anujan Varma, Chuan Cheng Pan, Patrick C. McCarthy, Hanh Hoang
  • Publication number: 20200143088
    Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit.
    Type: Application
    Filed: September 27, 2018
    Publication date: May 7, 2020
    Applicant: Xilinx, Inc.
    Inventors: Ravi Sunkavalli, Anujan Varma, Chuan Cheng Pan, Patrick C. McCarthy, Hanh Hoang
  • Patent number: 10505860
    Abstract: A scheduling system includes a request masking circuit configured to receive a plurality of original requests for priority arbitration among a plurality of entries, the plurality of original requests include a last original request and a first original request following the last original request. A last mask associated with a last grant result for the last original request is received from a mask generator circuit. A first masked request is generated by applying the last mask to the first original request. A request selection circuit is configured to generate a first selected request based on the first original request and the first masked request. The mask generator circuit is configured to generate a first mask based on the first selected request. The first mask is associated with a first grant result for the first original request.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 10, 2019
    Assignee: XILINX, INC.
    Inventors: Chuan Cheng Pan, Kiran S. Puranik
  • Patent number: 9100015
    Abstract: Finding the first bit that is set in an n-bit input word includes generating n n-bit patterns from an n-bit input word. If the bit at one bit position of the input word has a logic 1 value, a corresponding pattern has a logic 1 value in a corresponding bit position and in each bit position left of the corresponding bit position, and a logic 0 value in each bit position right of the corresponding bit position. If the bit at the one bit position of the input word has a logic 0 value, the corresponding pattern has a logic 0 value in every bit position. The n patterns are combined into one merged n-bit pattern. An output n-bit pattern is generated from the merged n-bit pattern. The output pattern has a logic 1 value in one bit position that is the same as the rightmost bit position of the input word having a logic 1 value, and a logic 0 value in every other bit position.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: August 4, 2015
    Assignee: XILINX, INC.
    Inventors: Chuan Cheng Pan, Ashish Gupta, Siva Prasad Gadey