Patents by Inventor Chuan-Cheng Tsou

Chuan-Cheng Tsou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250185354
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of fin structures, a gate oxide layer and a gate electrode layer. The fin structures are disposed on the substrate. The gate oxide layer is formed on the fin structures. The gate electrode layer covers the gate oxide layer and is substantially perpendicular to the fin structures, wherein the fin structures include a first type of fin and a second type of fin, and the gate oxide layer includes a first gate oxide portion and a second gate oxide portion, the first gate oxide portion covers the first type of fin, and the second gate oxide portion covers the second type of fin.
    Type: Application
    Filed: December 1, 2023
    Publication date: June 5, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Cheng Tsou, Tsung-Jing Wu, Sung-Hsin Yang, Jung-Chi Jeng, Chen-Chieh CHIANG, Ling-Sung WANG
  • Publication number: 20250142940
    Abstract: A method for manufacturing a semiconductor device includes: forming a first fin portion and a second fin portion on a semiconductor substrate, the first fin portion and the second fin portion being spaced apart from each other; and forming a first gate dielectric layer and a second gate dielectric layer on the first fin portion and the second fin portion, respectively, the first gate dielectric layer having a first thickness, the second gate dielectric layer having a second thickness different from the first thickness.
    Type: Application
    Filed: October 26, 2023
    Publication date: May 1, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chuan-Cheng TSOU, Po-Yuan SU, Sung-Hsin YANG, Jung-Chi JENG, Chen-Chieh CHIANG
  • Publication number: 20250079336
    Abstract: A stress modulating device including a semiconductor substrate, a first insulating layer formed over a first side of the semiconductor substrate, a second insulating layer formed over the first insulating layer, a third insulating layer formed over a second side of the semiconductor substrate, a fourth insulating layer formed over the third insulating layer, and a fifth insulating layer formed over the fourth insulating layer for incorporation in multi-stack package assemblies for reducing stress, strain, and/or warpage on the active elements within the package assembly.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Inventors: Sung-Hsin YANG, Jen-Yuan CHANG LIN, Chen-Chieh CHIANG, Chuan-Cheng TSOU
  • Publication number: 20250054873
    Abstract: Implementations described herein provide various implementations of gate based alignment patterns for semiconductor process alignment of a substrate on which semiconductor devices are manufactured. In some implementations described herein, a gate based alignment pattern may be included in an alignment mark region in a semiconductor device that is manufactured on the substrate. The alignment mark region may include a plurality of gate structures that are etched to form gate based alignment pattern. The use of the gate based alignment pattern may reduce the likelihood of and/or may prevent the gate based alignment pattern from becoming obscured or covered by residual material byproducts from one or more semiconductor processing operations that are performed to form various layers and/or structures of the semiconductor device.
    Type: Application
    Filed: August 8, 2023
    Publication date: February 13, 2025
    Inventors: Sung-Hsin YANG, Chuan-Cheng TSOU, Chen-Chieh CHIANG
  • Publication number: 20240429260
    Abstract: Embodiments of the present disclosure relate to methods for forming a film stack during fabrication or bonding process. The film stack according to present disclosure may reduce wet dip attacking to semiconductor substrate during bonding, such as bonding between an image sensor substrate and a logic device substrate. The film stack according to the present disclosure may be used to modulate stress and wafer warpage to improve bonding adhesion and device performance during various packaging schemes, such as CoWoS, SoIC, or the like. The film stack according to the present disclosure may be used to improve bonding process and device performance in both wafer-to-wafer bonding and die-to-die bonding.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 26, 2024
    Inventors: Chuan-Cheng Tsou, Sung-Hsin Yang, Jung-Chi Jeng, Chen-Chieh Chiang, Ru-Shang Hsiao, Ling-Sung Wang