Patents by Inventor Chuan-Chi CHOU

Chuan-Chi CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11839075
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: December 5, 2023
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chih-Jung Ni, Chuan-Chi Chou, Yao-Ting Tsai
  • Publication number: 20220189975
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure disposed on the substrate, an inter-gate dielectric layer disposed on the floating gate structure, and a control gate structure disposed on the inter-gate dielectric layer. The control gate structure includes an electrode layer disposed on the inter-gate dielectric layer, a contact layer disposed on the electrode layer, and a cap layer disposed on the contact layer. The first spacer is disposed on a sidewall of the control gate structure and covering the electrode, the contact layer and the cap layer. A bottom surface of the first spacer is positioned between a bottom surface and a top surface of the electrode layer.
    Type: Application
    Filed: March 3, 2022
    Publication date: June 16, 2022
    Inventors: Chih-Jung NI, Chuan-Chi CHOU, Yao-Ting TSAI
  • Patent number: 11302705
    Abstract: The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: April 12, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Chih-Jung Ni, Chuan-Chi Chou, Yao-Ting Tsai
  • Publication number: 20200152647
    Abstract: The present invention includes a semiconductor structure having a substrate, a gate structure, and a first spacer. The gate structure includes a floating gate structure, an inter-gate dielectric layer, and a control gate structure. The floating gate structure is disposed on the substrate. The inter-gate dielectric layer is disposed on the floating gate structure. The control gate structure is deposited on the inter-gate dielectric layer and includes an electrode layer, a contact layer and a cap layer. The electrode layer is disposed on the inter-gate dielectric layer. The contact layer is disposed on the electrode layer. The cap layer is disposed on the contact layer. The first spacer is disposed on sidewalls of the control gate structure and covers the electrode layer, the contact layer, and the cap layer. Furthermore, the bottom surface of the first spacer is disposed between the bottom surface and the top surface of the electrode layer.
    Type: Application
    Filed: August 29, 2019
    Publication date: May 14, 2020
    Inventors: Chih-Jung NI, Chuan-Chi CHOU, Yao-Ting TSAI