Abstract: A transmission control protocol (TCP) flow control method is provided, which comprises: sending a data packet from a packet processor to a receiver and storing a copy of the data packet; receiving a current ACK packet with a current packet number; determining whether the current packet number is identical to a last packet number and whether a last substitute ACK packet generated by the input ACK filter exists; and performing steps respectively corresponding to different results of this determination to avoid TCP congestion control timely. A TCP flow control device performing the method is also disclosed.

Abstract: A portable electronic device including a first body, a second body, a pivot element, a heat source, a first flexible heat conductive element, and a flip cover is provided. The pivot element is connected to the second body, and the second body is pivotally connected to the first body through the pivot element. The heat source is disposed in the first body. The first flexible heat conductive element is thermally coupled to the heat source and extends toward the pivot element from the heat source. The first flexible heat conductive element passes through the pivot element and extends into the inside of the second body and is thus thermally coupled to the second body. The flip cover is pivotally connected to the first body and located on a moving path of the pivot element.

Abstract: An improved method of patterning resist protective dielectric layer and preferably protective silicon dioxide layer is described. The method consists of two sequential etching steps, the first one being a timed plasma etching process and the second one being a timed wet etching process. Plasma etching is used to remove approximately 70%–90% of the RPO film thickness and wet etching is used to remove the remaining 10%–30% of the film thickness. The two-step etching process achieves superior dimensional control, a non-undercut profile under the resist mask and prevents resist mask peeling from failure of adhesion at the mask/RPO film interface. The improved method has wide applications wherever and whenever RPO film is used in the process flow for fabricating semiconductor devices.

Abstract: A method of forming a narrow diameter opening in an insulator layer, featuring a vertical shape profile, has been developed. Using a photoresist shape as an etch mask a first plasma procedure is used to form an initial opening, with a tapered profile shape, in the insulator layer exposing a portion of the top surface of an underlying stop layer. The first plasma procedure results in formation of a thin polymer layer located at the bottom of the initial opening. A second plasma procedure performed in situ, results in deposition of additional polymer layer, comprised of carbon and fluorine, at the bottom of the initial opening. This is followed by a third plasma procedure, performed in situ in an oxygen plasma, removing polymer and releasing fluorine based radicals which etch portions of insulator layer exposed at the bottom of the initial opening, resulting in a final opening featuring a vertical profile shape.

Abstract: A temperature-controlled focus ring assembly for use in a plasma chamber that includes a focus ring surrounding a wafer pedestal for confining plasma ions to a top surface of a wafer positioned on the wafer pedestal; a heat transfer means in intimate contact with the focus ring for decreasing or increasing the temperature of the focus ring; and a controller for controlling the temperature of the focus ring to a predetermined value. The invention further discloses a method for operating a plasma chamber equipped with a temperature-controlled focus ring assembly.

Abstract: An improved method of patterning resist protective dielectric layer and preferably protective silicon dioxide layer is described. The method consists of two sequential etching steps, the first one being a timed plasma etching process and the second one being a timed wet etching process. Plasma etching is used to remove approximately 70%-90% of the RPO film thickness and wet etching is used to remove the remaining 10%-30% of the film thickness. The two-step etching process achieves superior dimensional control, a non-undercut profile under the resist mask and prevents resist mask peeling from failure of adhesion at the mask/RPO film interface. The improved method has wide applications wherever and whenever RPO film is used in the process flow for fabricating semiconductor devices.

Abstract: A temperature-controlled focus ring assembly for use in a plasma chamber that includes a focus ring surrounding a wafer pedestal for confining plasma ions to a top surface of a wafer positioned on the wafer pedestal; a heat transfer means in intimate contact with the focus ring for decreasing or increasing the temperature of the focus ring; and a controller for controlling the temperature of the focus ring to a predetermined value. The invention further discloses a method for operating a plasma chamber equipped with a temperature-controlled focus ring assembly.

Abstract: A new method for detecting blind holes in the contact layer of a multi-chip semiconductor test wafer makes use of the fact that if the hole is not a blind hole, a subsequent etch step extends the hole a predetermined distance into the layer immediately underlying the contact layer. After a predetermined number of holes have been etched through the contact layer and for a predetermined distance into the layer underlying the contact layer, the contact layer is stripped to expose the holes in the underlying layer. These holes are scanned optically by a commercial apparatus that ordinarily detects wafer defects that resemble the holes. The missing holes are detected by comparing the holes of different chips on the test wafer. The test is particularly useful with a high density plasma etch because these holes typically have a very small diameter in relation to the thickness of the contact layer.

Abstract: A method of fabricating doped polysilicon structures comprising the following steps. A substrate is provided and an undoped polysilicon layer is formed over the substrate. The undoped polysilicon layer is patterned to form at least one undoped polysilicon structure within an N area and at least one undoped polysilicon structure within a P area. The at least one undoped polysilicon structure within the N area is masked, leaving exposed an upper portion of the other at least one undoped polysilicon structure within the P area. The exposed at least one undoped polysilicon structure within the P area is doped to form a P-doped polysilicon structure. An upper portion of the masked at least one undoped polysilicon structure within the N area is unmasked and exposed, and the P-doped polysilicon structure is masked. The exposed at least one undoped polysilicon structure within the N area is doped to form an N-doped polysilicon structure to complete fabrication of the doped polysilicon structures.