Abstract: A capacitor structure including a substrate, a capacitor, a second dielectric layer, a first conductive layer, and a second conductive layer is provided. The capacitor includes first electrode layers, at least one second electrode layer, and a first dielectric layer. The first electrode layers and the at least one second electrode layer are alternately disposed on the substrate. The first dielectric layer is disposed between the first electrode layer and the second electrode layer. The second dielectric layer has first openings and at least one second opening. The first openings expose the first electrode layers. The second opening exposes the second electrode layer. The first conductive layer is electrically connected to the first electrode layers. The first conductive layer is a single conductive layer disposed on the second dielectric layer and extending into the first openings. The second conductive layer is electrically connected to the second electrode layer.

Abstract: A capacitor structure including a substrate, a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a third electrode, and a stress balance layer is provided. The substrate has trenches and a pillar portion located between two adjacent trenches. The first electrode is disposed on the substrate, on the pillar portion, and in the trenches. The first dielectric layer is disposed on the first electrode and in the trenches. The second electrode is disposed on the first dielectric layer and in the trenches. The second dielectric layer is disposed on the second electrode and in the trenches. The third electrode is disposed on the second dielectric layer and in the trenches. The third electrode has a groove, and the groove is located in the trench. The stress balance layer is disposed in the groove.

Abstract: A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.

Abstract: A capacitor structure including a substrate, a first electrode, a first dielectric layer, a second electrode, a second dielectric layer, a third electrode, and a stress balance layer is provided. The substrate has trenches and a pillar portion located between two adjacent trenches. The first electrode is disposed on the substrate, on the pillar portion, and in the trenches. The first dielectric layer is disposed on the first electrode and in the trenches. The second electrode is disposed on the first dielectric layer and in the trenches. The second dielectric layer is disposed on the second electrode and in the trenches. The third electrode is disposed on the second dielectric layer and in the trenches. The third electrode has a groove, and the groove is located in the trench. The stress balance layer is disposed in the groove.

Abstract: A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.

Abstract: A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.

Abstract: The present invention provides a method of assembling an LCD panel, an interface apparatus, and an assembling apparatus. In this invention, the first panel of the LCD panel is mounted on the interface apparatus before being pressed to the second panel of the LCD panel. Therefore, the complexity of the assembly room can be simplified and the cycle time in the assembly room can be shortened by moving the processes of flatly attaching and separating panels out of the assembly room. The interface apparatus is easier to be processed than a glass substrate during operation. The design of the interface apparatus can simplify the mechanisms in the assembly room and shorten the cycle time. The usage of the interface apparatus can reduce the alignment error caused by nonsynchronization of releasing static electricity suckers.

Abstract: A container includes a top wall, side walls, and a bottom wall, designed to enclose a space for storing an insulating object, the top, side and bottom walls having internal surfaces facing the enclosed space and external surface facing away from the enclosed space; and a metallic coating layer disposed on and substantially covering external surfaces of the top, side and bottom walls.

Abstract: A method is disclosed for aligning wafers independent of the planarity of layers that are formed on a wafer. In prior art, it is found that when aligning wafers from the front or device side, the alignment of the masks vary because of the variations on the topography of the particular layer in process. Since the topography of a layer is influenced by the cumulative effect of the number of underlying features that are disposed on top of each other, severe misalignments can occur causing defective parts. The problem is eliminated by depositing an infrared reflective (IR) coating over alignment marks formed on oxide layer covering the devices on a wafer, and performing alignment with respect to the reflective marks by projecting IR energy through an IR transparent stage placed under the backside of the wafer and using an IR microscope.