Abstract: A gate driving device and an operating method are provided. The gate driving device includes a plurality of gate driving circuits and a control circuit. The gate driving circuits generate a plurality of gate driving signals having different timing. The control circuit is coupled to a plurality of candidate gate driving circuits among the gate driving circuits. The control circuit selects one of the candidate gate driving circuits as an initial stage gate driving circuit per one scanning cycle. A series connection mode between the gate driving circuits is changed in response to a scan selection signal.

Abstract: A clock data recovery (CDR) circuit includes: a band select circuit, a low dropout regulator (LDO), a charge pump and a voltage-controlled oscillator (VCO), wherein the band select circuit is arranged to generate a digital signal according to at least a reference voltage; the LDO is arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO; the charge pump is arranged to generate a control voltage according to at least a part of the digital signal; and the VCO is arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.

Abstract: An output amplifier of a source driver and a control method thereof are provided. The output amplifier includes a first switch circuit, a second switch circuit, a third switch circuit, a first input stage circuit, a second input stage circuit, a first active load circuit, a second active load circuit, a first positive output stage circuit, a first negative output stage circuit, a second positive output stage circuit and a second negative output stage circuit. In a first display stage of the control method, the first switch circuit outputs a positive reference signal through a first output terminal and outputs a negative reference signal through a second output terminal. In a second display stage of the control method, the signals outputted by the first output terminal and the second output terminal are exchanged.

Abstract: A clock data recovery (CDR) circuit includes: a band select circuit, a low dropout regulator (LDO), a charge pump and a voltage-controlled oscillator (VCO), wherein the band select circuit is arranged to generate a digital signal according to at least a reference voltage; the LDO is arranged to regulate a ground voltage, wherein the LDO adjusts an operating band of the LDO by receiving at least a part of the digital signal to adjust a bias current of an amplifier of the LDO; the charge pump is arranged to generate a control voltage according to at least a part of the digital signal; and the VCO is arranged to generate a clock signal according to the control voltage, wherein the VCO adjusts an operating band of the CDR circuit by receiving at least a part of the digital signal to adjust a bias current of the VCO.

Abstract: A driving apparatus and a method for driving a display panel thereof are provided. The driving apparatus includes an output buffer, a switch, an adjusting circuit, a digital-to-analog converter and a code detecting unit. The output buffer provides an output voltage to a load according to a static current determining a speed of the output voltage reaching a target voltage for driving the load. The switch is coupled between the output buffer and the load in series, and is turned on or off according to a control signal. The code detecting unit detects an input code. The adjusting circuit determines whether the input code varies when the control signal is enabled, and disables a high driving ratio signal when the input code does not vary when the control signal is enabled. An enabling period of the high driving ratio signal is different from an enabling period of the control signal.

Abstract: An output amplifier of a source driver and a control method thereof are provided. The output amplifier includes a first switch circuit, a second switch circuit, a third switch circuit, a first input stage circuit, a second input stage circuit, a first active load circuit, a second active load circuit, a first positive output stage circuit, a first negative output stage circuit, a second positive output stage circuit and a second negative output stage circuit. In a first display stage of the control method, the first switch circuit outputs a positive reference signal through a first output terminal and outputs a negative reference signal through a second output terminal. In a second display stage of the control method, the signals outputted by the first output terminal and the second output terminal are exchanged.

Abstract: A driving apparatus and a method for driving a display panel thereof are provided. The driving apparatus includes an output buffer, a switch, an adjusting circuit, a digital-to-analog converter and a code detecting unit. The output buffer provides an output voltage to a load according to a static current determining a speed of the output voltage reaching a target voltage for driving the load. The switch is coupled between the output buffer and the load in series, and is turned on or off according to a control signal. The code detecting unit detects an input code. The adjusting circuit determines whether the input code varies when the control signal is enabled, and disables a high driving ratio signal when the input code does not vary when the control signal is enabled. An enabling period of the high driving ratio signal is different from an enabling period of the control signal.

Abstract: A voltage sensing circuit is provided. The voltage sensing circuit includes two differential amplifiers and a buffer. The first differential amplifier receives a first input voltage and a first reference voltage and provides a first current and a second current according to the difference between the first input voltage and the first reference voltage. The second differential amplifier receives a second input voltage and a second reference voltage and provides a third current and a fourth current according to the difference between the second input voltage and the second reference voltage. The buffer is coupled to the two differential amplifiers. The buffer generates an output voltage based on the first current, the second current, the third current, and the fourth current.

Abstract: A voltage sensing circuit is provided. The voltage sensing circuit includes two differential amplifiers and a buffer. The first differential amplifier receives a first input voltage and a first reference voltage and provides a first current and a second current according to the difference between the first input voltage and the first reference voltage. The second differential amplifier receives a second input voltage and a second reference voltage and provides a third current and a fourth current according to the difference between the second input voltage and the second reference voltage. The buffer is coupled to the two differential amplifiers. The buffer generates an output voltage based on the first current, the second current, the third current, and the fourth current.

Abstract: A gamma operational amplifier circuit, a source driver, and a method for eliminating voltage offset are disclosed. The gamma operational amplifier circuit includes a first switch circuit, a second switch circuit, a first operational amplifier and a second operational amplifier. The source driver includes the gamma operational amplifier circuit, a resistor string and a digital-to-analog converter. The method for eliminating voltage offset includes a positive polarity control stage and a negative polarity control stage. In the method for eliminating voltage offset, the positive polarity control stage and the negative polarity control stage control the first switch circuit and the second switch circuit to change paths at which a first reference voltage and a second reference voltage pass through to enable the first reference voltage and a second reference voltage to pass different operational amplifiers in different polarity control stage.

Abstract: A liquid crystal display device includes a controlling chip and a circuit wire electrically connected to the controlling chip, both disposed on a printed circuit board, and N wire sets and 2N driving chips, all disposed on a glass substrate. N is a positive integer. A characteristic impedance of the circuit wire is equivalent to an output impedance of the controlling chip. The k-th wire set includes 2k?1 peripheral wires, a midpoint of the first peripheral wire in the first wire set is electrically connected to the circuit wire, characteristic impedances of the peripheral wires in the k-th wire set are 2k times the output impedance, k is an integer, and 1?k?N. The driving chips are electrically connected to the N-th wire set, and each of the driving chips adjusts the input impedance according to a control information, so as to make the input impedance 2N times the output impedance.

Abstract: A start circuit including a load unit, a first switch, a second switch and a reset control circuit is provided. The load unit receives a power voltage. The first switch is electrically connected between a first end of the load unit and a ground, and receives a node voltage from a reference circuit. The second switch has a first end electrically connected to the reference circuit, a second end electrically connected to the ground, and a control end electrically connected to the second end of the load unit. The second switch determines whether to provide a start voltage to the reference circuit according to a conducting state thereof. The reset control circuit provides a discharge path between a control end of the first switch and the ground, and conducts the discharge path according to the power voltage during a period when the power voltage is smaller than a threshold voltage.

Abstract: A liquid crystal display device includes a controlling chip and a circuit wire electrically connected to the controlling chip, both disposed on a printed circuit board, and N wire sets and 2N driving chips, all disposed on a glass substrate. N is a positive integer. A characteristic impedance of the circuit wire is equivalent to an output impedance of the controlling chip. The k-th wire set includes 2k?1 peripheral wires, a midpoint of the first peripheral wire in the first wire set is electrically connected to the circuit wire, characteristic impedances of the peripheral wires in the k-th wire set are 2k times the output impedance, k is an integer, and 1?k?N. The driving chips are electrically connected to the N-th wire set, and each of the driving chips adjusts the input impedance according to a control information, so as to make the input impedance 2N times the output impedance.

Abstract: A start circuit including a load unit, a first switch, a second switch and a reset control circuit is provided. The load unit receives a power voltage. The first switch is electrically connected between the load unit and a ground, and receives a node voltage from the reference circuit. The second switch has a first end electrically connected to the reference circuit, a second end electrically connected to the ground, and a control end electrically connected to the second end of the load unit. The second switch determines whether to provide a start voltage to a reference circuit according to a conducting state thereof. The reset control circuit provides a discharge path between the control end of the first switch and the ground, and conducts the discharge path according to the power voltage during a period when the power voltage is smaller than a threshold voltage.

Abstract: A source driver device includes a de-skew block device for receiving image data and clock signals, the de-skew block device has a receiver for receiving a clock signal and image data, a delay lock loop for generating a plurality of sub-clock signals, each having different delay times increasing in order, based on the clock signal, an edge detection unit for finding an edge of the data by the sub-clocks, and selecting one from the sub-clocks based on the edge as a de-skewed clock, and a data de-skew unit for sampling the image data by the de-skewed clock signal to output de-skewed image data and the de-skewed clock signal, and a plurality of channels for receiving the de-skewed image data and the de-skewed clock signal to drive an LCD panel.

Abstract: A source driver device for driving a display panel includes a gamma voltage generator having a storage element and a plurality of gamma digital-to-analog converters, a data digital-to-analog converter coupled to the gamma voltage generator, and a receiver for receiving input display data from a data bus, for parsing the input display data to transmit generated display data to the data digital-to-analog converter, and for transmitting a plurality of gamma data signals to the storage element, wherein each of the plurality of gamma digital-to-analog converters receive the plurality of gamma data signals from the storage element for generating a plurality of reference voltage signals based on the corresponding gamma data signals, and wherein the data digital-to-analog converter is coupled to the receiver to receive the generated display data, according to the generated plurality of reference voltage signals generated from the gamma digital-to-analog converters, and to generate a driving voltage signal based on th