Abstract: A hardmask structure and a method of forming a semiconductor structure are provided. The hardmask structure includes a first ashable hardmask, a first dielectric antireflective coating, and a second ashable hardmask. The first dielectric antireflective coating is disposed on the first ashable hardmask. The second ashable hardmask is disposed on the first dielectric antireflective coating. A stress of the first ashable hardmask is from about ?100 MPa to about 100 MPa.

Abstract: A system for generating 3D indoor scenes from text input is provided. It includes a user interface, a text processing module, a scene code generator, a layout generation module, an appearance generation module, a NeRF module, and a PeRF module. The user inputs text describing a room, which is processed into scene codes. These codes guide the generation of a 3D layout using oriented bounding boxes, ensuring spatial integrity. The appearance module then creates a visual representation with a panoramic image. The NeRF module constructs a base 3D model, which is refined by the PERF module for enhanced visual coherence.

Abstract: The present disclosure provides a method for preparing a semiconductor structure using the hardmask structure. The method includes forming a conductive layer on a substrate; forming a first ashable hardmask layer on the conductive layer; forming a first anti-reflection coating on the first ashable hardmask layer; forming a second ashable hardmask layer on the first anti-reflection coating, wherein a modulus of the first ashable hardmask layer is greater than a modulus of the second ashable hardmask layer; etching the first ashable hardmask layer, the first anti-reflection coating, and the second ashable hardmask layer to transfer a first pattern to at least the first ashable hardmask layer; and etching the conductive layer according to the first ashable hardmask layer to form a patterned conductive layer.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a landing pad, and air gap protection structure. The bit line is disposed on the substrate. The isolation spacer is disposed on a side of the bit line. The isolation spacer includes an air gap. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure has an upper portion above a top surface of the landing pad and a lower portion below the upper portion. A ratio between a thickness of the lower portion and a thickness of the upper portion is greater than 0.6 and less than 0.8.

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, an isolation spacer, a landing pad, and air gap protection structure. The bit line is disposed on the substrate. The isolation spacer is disposed on a side of the bit line. The isolation spacer includes an air gap. The landing pad is disposed over the bit line. The air gap protection structure covers the landing pad and the air gap. The air gap protection structure has an upper portion above a top surface of the landing pad and a lower portion below the upper portion. A ratio between a thickness of the lower portion and a thickness of the upper portion is greater than 0.6 and less than 0.8.

Abstract: A semiconductor device includes a substrate, a gate electrode in the substrate, a channel region above the gate electrode, a gate dielectric layer between the gate electrode and the channel region, and at least two source/drain regions in contact with the channel region. The channel region includes at least one boron-carbon-nitrogen single-walled nanotube (BCN-SWNT).

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes: providing a semiconductor structure, in which the semiconductor structure includes alternatively disposed first nitride portions and second nitride portions wrapping portions of an oxide layer, a dielectric layer disposed between one of the first nitride portions and one of the second nitride portions, a top nitride surrounded by the one of the first nitride portions or the one of the second nitride portions, a filling material, and a cap layer disposed on the filling material; forming a plurality of trenches to expose the portions of the oxide layer wrapped by the first nitride portions and the second nitride portions; forming air gaps by removing the portions of the oxide layer; and conformally forming an encapsulating layer on inner sidewalls of the trenches to encapsulate the air gaps.

Abstract: A miniature circuit breaker for providing short circuit and overload protection is disclosed herein. The miniature circuit breaker features a field effect transistor (FET), which may be a depletion mode metal oxide semiconductor FET (D MOSFET), a junction field-effect transistor (JFET), or a silicon carbide JFET, the FET being connected to a bi-metallic switch, where the bi-metallic switch acts as a temperature sensing circuit breaker. In combination, the D MOSFET and bi-metallic switch are able to limit current to downstream circuit components, thus protecting the components from damage.

Abstract: A hardmask structure and a method of forming a semiconductor structure are provided. The hardmask structure includes a first ashable hardmask, a first dielectric antireflective coating, and a second ashable hardmask. The first dielectric antireflective coating is disposed on the first ashable hardmask. The second ashable hardmask is disposed on the first dielectric antireflective coating. A stress of the first ashable hardmask is from about ?100 MPa to about 100 MPa.

Abstract: A hardmask structure and a method of forming a semiconductor structure are provided. The hardmask structure includes a first ashable hardmask, a first dielectric antireflective coating, and a second ashable hardmask. The first dielectric antireflective coating is disposed on the first ashable hardmask. The second ashable hardmask is disposed on the first dielectric antireflective coating. A stress of the first ashable hardmask is from about ?100 MPa to about 100 MPa.

Abstract: The present disclosure provides a hardmask structure for preparing a semiconductor structure. The hardmask structure includes a first ashable hardmask layer, a first anti-reflection coating, and a second ashable hardmask layer. The first anti-reflection coating is disposed on the first ashable hardmask layer. The second ashable hardmask layer is disposed on the first anti-reflection coating. A modulus of the first ashable hardmask layer is greater than a modulus of the second ashable hardmask layer.

Abstract: The present disclosure provides a method for preparing a semiconductor structure using the hardmask structure. The method includes forming a conductive layer on a substrate; forming a first ashable hardmask layer on the conductive layer; forming a first anti-reflection coating on the first ashable hardmask layer; forming a second ashable hardmask layer on the first anti-reflection coating, wherein a modulus of the first ashable hardmask layer is greater than a modulus of the second ashable hardmask layer; etching the first ashable hardmask layer, the first anti-reflection coating, and the second ashable hardmask layer to transfer a first pattern to at least the first ashable hardmask layer; and etching the conductive layer according to the first ashable hardmask layer to form a patterned conductive layer.

Abstract: A memory device includes a bottom electrode, an insulating layer, and a top electrode. The bottom electrode includes a plurality of carbon nanotubes. The insulating layer is disposed over the plurality of carbon nanotubes. The top electrode includes a graphene layer separated from the plurality of carbon nanotubes by the insulating layer.

Abstract: A miniature circuit breaker for providing short circuit and overload protection is disclosed herein. The miniature circuit breaker features a field effect transistor (FET), which may be a depletion mode metal oxide semiconductor FET (D MOSFET), a junction field-effect transistor (JFET), or a silicon carbide JFET, the FET being connected to a bi-metallic switch, where the bi-metallic switch acts as a temperature sensing circuit breaker. In combination, the D MOSFET and bi-metallic switch are able to limit current to downstream circuit components, thus protecting the components from damage.

Abstract: A method of capacitance structure manufacturing includes following operations. A plurality of insulating tubes is formed over a substrate and perpendicular to the substrate. A first supporting layer and a second supporting layer above the first supporting layer are formed and connect the insulating tubes. The first supporting layer protrudes from the second supporting layer. Conductive material is filled in the insulating tubes to form rod capacitors forming a capacitor array and the capacitor array is covered by an oxide layer from its top to the substrate. The oxide layer is formed along the first supporting layer and the second supporting layer such that the oxide layer extends along a direction having an angle with respect to the substrate.

Abstract: A surge protection apparatus may include an input terminal; an output terminal, the output terminal electrically coupled to the input terminal; a ground terminal, the ground terminal electrically coupled to the input terminal and output terminal; a positive temperature coefficient (PTC) fuse, the PTC fuse connected in electrical series between the input terminal and output terminal; a crowbar device, the crowbar device electrically connected to the ground terminal and output terminal, wherein the crowbar device is in electrical series with the PTC fuse between the input terminal and ground terminal; and a central frame portion, the central frame portion electrically coupled to the input terminal, output terminal and ground terminal, wherein the crowbar device is disposed on a first side of the central frame portion and the PTC fuse is disposed on a second side of the central frame portion, opposite the first side.

Abstract: A miniature circuit breaker for providing short circuit and overload protection is disclosed herein. The miniature circuit breaker features a field effect transistor (FET), which may be a depletion mode metal oxide semiconductor FET (D MOSFET), a junction field-effect transistor (JFET), or a silicon carbide JFET, the FET being connected to a bi-metallic switch, where the bi-metallic switch acts as a temperature sensing circuit breaker. In combination, the D MOSFET and bi-metallic switch are able to limit current to downstream circuit components, thus protecting the components from damage.

Abstract: A method of capacitance structure manufacturing includes following operations. A plurality of insulating tubes is formed over a substrate and perpendicular to the substrate. A first supporting layer and a second supporting layer above the first supporting layer are formed and connect the insulating tubes. The first supporting layer protrudes from the second supporting layer. Conductive material is filled in the insulating tubes to form rod capacitors forming a capacitor array and the capacitor array is covered by an oxide layer from its top to the substrate. The oxide layer is formed along the first supporting layer and the second supporting layer such that the oxide layer extends along a direction having an angle with respect to the substrate.

Abstract: An ultra-low clamping voltage Surge Protection Module (SPM) is disclosed which utilizes a depletion mode MOSFET (D MOSFET). The SPM may be part of a circuit or a device and includes a primary protection stage and a secondary protection stage, with the D MOSFET being connected between the two stages. The SPM may include a single D MOSFET, dual D MOSFETs, or multiple D MOSFETs and the primary and secondary protection stages may be implemented with a number of different components. The SPM using D MOSFET(s) exhibits improved surge protection over circuits using inductors.

Abstract: A capacitance structure includes a substrate, a plurality of rod capacitors and an oxide layer. The rod capacitors are located on a top surface of the substrate and form a capacitor array. The oxide layer covers a top and a side of the capacitor array and a portion of the substrate. The rod capacitors extend along a first direction perpendicular to a second direction in which the top surface of the substrate extends. The oxide layer extends from the top of the capacitor array to the substrate along a third direction, and an angle is formed between the first and third directions.