Abstract: A card edge connector includes: a connector base having a card slot and plural terminals; a latch located at one end of the connector base for locking a card; and a releasing member. The releasing member includes two levers and a moving member, the levers are connected with the connector base in a pivoting manner, a first end of the lever is connected with the latch and an opposite second end of the lever is coupled to the moving member, wherein when the card is inserted into the slot and presses against the moving member downwards, the moving member drives the second ends of the levers to move downward, resulting in the first ends moving upwards to push the latch to lock with the card, and when the card is pulled out the moving member resets and drives the levers to release the latch from the card.

Abstract: The present disclosure relates to a circuit unit, a logic circuit, a processor, and a computing apparatus. A circuit unit is provided, including: an output terminal (OUT); an output stage (105), configured to provide an output signal to the output terminal; a first node (A), to which an input of the output stage is connected; and a feedback stage (107) that receives the output signal at the output terminal and selectively provides feedback to the node. A logic circuit is further provided, including an input stage that receives a signal input, and the circuit unit. The first node receives a signal based on an output of the input stage.

Abstract: The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.

Abstract: The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.

Abstract: The present disclosure relates to a D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.

Abstract: Techniques pertaining to an analog sample circuit are disclosed. One embodiment of the analog sample circuit shows characteristics of low distortion and high linearity, which can be used in many circuits including integrated circuits (IC). In a switch circuit or an analog sample circuit of one embodiment, a constant voltage module is configured to stabilize the gate-source voltage of the PMOSFET switch as the sample switch, so that the gate-resource voltage of the PMOSFET switch doesn't vary with the input signal Vin; a switch circuit is configured to ensure that the switch circuit or the analog sample circuit is capable of processing the input signal lower than a minimum voltage in the circuit.

Abstract: Techniques pertaining to an analog sample circuit are disclosed. One embodiment of the analog sample circuit shows characteristics of low distortion and high linearity, which can be used in many circuits including integrated circuits (IC).