Abstract: An embodiment of the present invention discloses a power saving outlet system and a method for controlling thereof. The power saving outlet system includes a main outlet, at least one auxiliary outlet, a current detection unit, and a control unit. The current detection unit generates a current detection signal according to an operational current of the main device. And the control unit determines if the current detection signal is smaller than the threshold value to selectively cause an electrical power to be delivered from the external power source to the auxiliary device.

Abstract: A method of determining reliability of semiconductor products. The method comprises providing a semiconductor wafer, which comprises a plurality of MOS transistors formed on its surface, and placing the semiconductor wafer in an environment of a stress temperature during a testing time period. The MOS transistor is simultaneously stressed with a stress voltage. A plurality of testing points are defined in the testing time, and the threshold voltage shift of the MOS transistor is measured at each testing point for establishing a group of experimental data. Finally, a relationship model of threshold voltage shift (&Dgr;Vth) vs. time (t) is provided, and the group of experimental data and the relationship model are used to depict a relation curve for predicting the threshold voltage shift of the MOS transistor when exceeding the testing time.

Abstract: A method of determining reliability of semiconductor products. The method comprises providing a semiconductor wafer, which comprises a plurality of MOS transistors formed on its surface, and placing the semiconductor wafer in an environment of a stress temperature during a testing time period. The MOS transistor is simultaneously stressed with a stress voltage. A plurality of testing points are defined in the testing time, and the threshold voltage shift of the MOS transistor is measured at each testing point for establishing a group of experimental data. Finally, a relationship model of threshold voltage shift (&Dgr;Vth) vs. time (t) is provided, and the group of experimental data and the relationship model are used to depict a relation curve for predicting the threshold voltage shift of the MOS transistor when exceeding the testing time.

Abstract: The present invention relates to a method which introduce a parasitic series resistance for solving electrostatic discharge voltages by using transmission line pulse method and least square error solution method. In present invention, we introduce a parasitic series resistance, Rs, into the equation which presents the correlation between the transmission line pulse method and human body model. The equation is then rewritten as electrostatic discharge voltage=electrostatic discharge current×(the human body equivalent resistance+the parasitic series resistance) We can obtain the optimal parasitic series resistance and electrostatic discharge voltage by using the least square error solution method.

Abstract: This invention relates to a method for forming a gate dielectric layer, and, more particularly, to a method for treating a base oxide layer by using a remote plasma nitridation procedure and a thermal annealing treatment in turn to form the gate dielectric layer. The first step of the present invention is to form a base oxide layer on a substrate of a wafer. The base oxide layer can be formed using any kind of method. Then nitrogen ions are introduced into the base oxide layer using the remote plasma nitridation procedure to form a remote plasma nitrided oxide layer. Finally, the wafer is placed in a reaction chamber which comprises oxygen (O2) or nitric monoxide (NO) to treat the remote plasma nitrided oxide layer using the thermal annealing procedure and the gate dielectric layer of the present invention is formed.

Abstract: The present invention relates to a method which introduce a parasitic series resistance for solving electrostatic discharge voltages by using transmission line pulse method and least square error solution method. In present invention, we introduce a parasitic series resistance, Rs, into the equation which presents the correlation between the transmission line pulse method and human body model.