Patents by Inventor Chuan-Hsiang Chen

Chuan-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Mapping table updating method, memory controlling circuit unit and memory storage device
    Patent number: 10713178
    Abstract: A mapping table updating method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: calculating a plurality of updated data counts of a plurality of updated logical units in at least one active physical erasing unit respectively according to a physical-logical mapping table; selecting a first updated logical unit from a plurality of updated logical units according to the plurality of updated data counts, and the number of the first updated logical unit is less than the number of the plurality of updated logical units; loading a first logical-physical mapping table corresponding to the first updated logical unit; and updating mapping information in the first logical-physical mapping table according to mapping information of the first updated logical unit in the physical-logical mapping table.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 14, 2020
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chia-Han Yen, Chuan-Hsiang Chen
  • MAPPING TABLE UPDATING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    Publication number: 20200151108
    Abstract: A mapping table updating method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: calculating a plurality of updated data counts of a plurality of updated logical units in at least one active physical erasing unit respectively according to a physical-logical mapping table; selecting a first updated logical unit from a plurality of updated logical units according to the plurality of updated data counts, and the number of the first updated logical unit is less than the number of the plurality of updated logical units; loading a first logical-physical mapping table corresponding to the first updated logical unit; and updating mapping information in the first logical-physical mapping table according to mapping information of the first updated logical unit in the physical-logical mapping table.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 14, 2020
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chia-Han Yen, Chuan-Hsiang Chen