Patents by Inventor Chuan-Hsien Fu

Chuan-Hsien Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8546890
    Abstract: An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: October 1, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Li Kuo, Chia-Chun Sun, Chuan-Hsien Fu, Chun-Liang Hou, Yun-San Huang
  • Publication number: 20110309424
    Abstract: A structure of a memory cell of a static random memory device and a process for fabricating the same are disclosed. The memory cell includes a substrate having an active region including an N-well and a shallow trench isolation structure; a first gate and a second gate formed over the substrate; a halo region, a LLD, and a source and drain region formed on two sides of the first gate; an interlevel dielectric layer covering the substrate, the first and second gates; and a contact penetrating the interlevel dielectric layer and extending to the source and drain region, no halo region is formed under the contact.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Inventors: Ming-Te WEI, Po-Chao Tsao, Jun-Chi Huang, Chia-Wei Huang, Chuan-Hsien Fu, Chih-Fang Tsai, Te-Hung Wu
  • Publication number: 20100127337
    Abstract: An inverter structure is disclosed. The inverter structure includes an NMOS transistor and a PMOS transistor. Preferably, the NMOS transistor includes an n-type gate electrode and an n-type source/drain region, and the PMOS transistor includes a p-type gate electrode and a p-type source/drain region. Specifically, the n-type gate electrode and the p-type gate electrode are physically separated and electrically connected by a conductive contact.
    Type: Application
    Filed: November 27, 2008
    Publication date: May 27, 2010
    Inventors: Chien-Li Kuo, Chia-Chun Sun, Chuan-Hsien Fu, Chun-Liang Hou, Yun-San Huang
  • Patent number: 7687206
    Abstract: The invention provides a mask pattern. The mask pattern comprises at least a continuous pattern. Each of the continuous patterns has a first pattern, a second pattern and a set of assistance patterns. The assistant patterns are located between the first pattern to the second pattern. The first pattern, the assistant patterns and the second pattern together form a closed opening.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: March 30, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Chuan-Hsien Fu, Chuen-Huei Yang, Chien-Li Kuo, Shu-Ru Wang, Yu-Lin Wang
  • Publication number: 20080220341
    Abstract: The invention provides a mask pattern. The mask pattern comprises at least a continuous pattern. Each of the continuous patterns has a first pattern, a second pattern and a set of assistance patterns. The assistant patterns are located between the first pattern to the second pattern. The first pattern, the assistant patterns and the second pattern together form a closed opening.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 11, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Hsien Fu, Chuen-Huei Yang, Chien-Li Kuo, Shu-Ru Wang, Yu-Lin Wang