Patents by Inventor CHUAN-HU LIN

CHUAN-HU LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230283309
    Abstract: The present invention discloses a signal receiving apparatus having phase compensation mechanism. A first and a second receiving path of a receiving circuit perform frequency down-conversion and analog-to-digital conversion on an input signal to generate a first and a second receiving signals. The first and the second receiving paths uses a RF training signal generated by a RF training signal generation circuit as the input signal when a phase compensation is performed, and use a data signal from an antenna circuit as the input signal when a beamforming signal receiving is performed. A phase difference calculation circuit of the receiving circuit performs cross-correlation operation on the first and the second receiving signals to generate a compensation signal according to a phase difference between the first and the second receiving paths.
    Type: Application
    Filed: December 6, 2022
    Publication date: September 7, 2023
    Inventors: HAO-HAN HSU, CHUAN-HU LIN, CHUNG-YAO CHANG
  • Publication number: 20230189327
    Abstract: A wireless device includes a time-sensitive queue, an access category queue, a controller, and a transmitter. The access category queue is associated with an access category and a link. The controller is coupled to the access category queue, and is used to acquire a transmission opportunity according to a set of contention parameters of the access category. The transmitter is coupled to the controller and the time-sensitive queue, and is used to when a transmission opportunity is acquired, if the time-sensitive queue contains data, generate a data frame according to the data in the time-sensitive queue, and transmit the data to another wireless device via a link.
    Type: Application
    Filed: June 23, 2022
    Publication date: June 15, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Chung-Yao Chang, Chuan-Hu Lin
  • Patent number: 10708032
    Abstract: Disclosed is a symbol timing determining device including: a symbol timing detecting circuit detecting a reception signal to obtain a first symbol timing, and shifting the first symbol timing to obtain a second symbol timing; an estimation signal generating circuit processing the reception signal according to the first and the second symbol timings respectively, so as to obtain a first and a second channel estimation frequency-domain signals; a channel estimation impulse response signal generating circuit generating a first and a second channel estimation impulse response time-domain signals according to the first and the second channel estimation frequency-domain signals respectively; a power measuring circuit measuring the energy of the first and the second channel estimation impulse response time-domain signals according to a predetermined signal region respectively; and a decision circuit selecting one of the first and the second symbol timings according to a relation of the measured energy.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chuan-Hu Lin, Chung-Yao Chang
  • Patent number: 10461776
    Abstract: A receiving device comprises an iterative decoder, a first determination unit and a control unit. The iterative decoder is for receiving at least one coded signal and for performing an iterative decoding on the at least one coded signal, to generate a plurality of decoded signals, wherein the plurality of decoded signals comprise a first decoded signal from a first iteration, a second decoded signal from a second iteration and a third decoded signal from a third iteration. The first determination unit is for determining whether the plurality of decoded signals diverge, to generate a first determination result. The control unit is for generating a control signal according to at least the first determination result, wherein the control signal indicates the iterative decoder whether to stop performing the iterative decoding on the at least one coded signal.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: October 29, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chuan-Hu Lin, Wei-Chieh Huang, Chia-Chun Tsui, Chung-Yao Chang
  • Patent number: 10382163
    Abstract: A receiving device comprises a channel estimation unit, for generating a plurality of channel estimates according to a plurality of reference signals; an eigenvalue computation unit, coupled to the channel estimation unit, for generating at least one eigenvalue corresponding to the plurality of channel estimates according to the plurality of channel estimates; a channel compensation unit, coupled to the eigenvalue computation unit, for generating a correlation compensation value for compensating the plurality of channels according to the at least one eigenvalue; a channel capacity computation unit, coupled to the eigenvalue computation unit and the channel compensation unit, for generating a channel capacity according to the at least one eigenvalue and the correlation compensation value; and a selection unit, coupled to the channel capacity computation unit, for determining a modulation and coding scheme (MCS) according to the channel capacity.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 13, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chuan-Hu Lin, Chung-Yao Chang
  • Patent number: 10355802
    Abstract: A method of cell search for a mobile device in a wireless communication system is provided. The method comprises performing a reception timing detection procedure, to obtain at least a possible reception time for a primary synchronization signal (PSS), performing a PSS hypothesis procedure, to generate three frequency-domain PSS sequences according to three root indexes each corresponding to a physical layer identity, and performing a secondary synchronization signal (SSS) coherent detection procedure, to calculate a SSS sequence according to each of the at least a possible reception time with the three frequency-domain PSS sequences, to obtain a physical layer cell identity group corresponding to the SSS sequence.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: July 16, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chung-Yao Chang, Chuan-Hu Lin
  • Publication number: 20190215143
    Abstract: Disclosed is a symbol timing determining device including: a symbol timing detecting circuit detecting a reception signal to obtain a first symbol timing, and shifting the first symbol timing to obtain a second symbol timing; an estimation signal generating circuit processing the reception signal according to the first and the second symbol timings respectively, so as to obtain a first and a second channel estimation frequency-domain signals; a channel estimation impulse response signal generating circuit generating a first and a second channel estimation impulse response time-domain signals according to the first and the second channel estimation frequency-domain signals respectively; a power measuring circuit measuring the energy of the first and the second channel estimation impulse response time-domain signals according to a predetermined signal region respectively; and a decision circuit selecting one of the first and the second symbol timings according to a relation of the measured energy.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 11, 2019
    Inventors: CHUAN-HU LIN, CHUNG-YAO CHANG
  • Publication number: 20180248563
    Abstract: A receiving device comprises an iterative decoder, for receiving at least one coded signal and for performing an iterative decoding on the at least one coded signal, to generate a plurality of decoded signals, wherein the plurality of decoded signals comprise a first decoded signal from a first iteration, a second decoded signal from a second iteration and a third decoded signal from a third iteration; a first determination unit, coupled to the iterative decoder, for determining whether the plurality of decoded signals diverge, to generate a first determination result; and a control unit, coupled to the first determination unit, for generating a control signal according to at least the first determination result, wherein the control signal indicates the iterative decoder whether to stop performing the iterative decoding on the at least one coded signal.
    Type: Application
    Filed: January 4, 2018
    Publication date: August 30, 2018
    Inventors: Chuan-Hu Lin, Wei-Chieh Huang, Chia-Chun Tsui, Chung-Yao Chang
  • Publication number: 20180205489
    Abstract: A receiving device comprises a channel estimation unit, for generating a plurality of channel estimates according to a plurality of reference signals; an eigenvalue computation unit, coupled to the channel estimation unit, for generating at least one eigenvalue corresponding to the plurality of channel estimates according to the plurality of channel estimates; a channel compensation unit, coupled to the eigenvalue computation unit, for generating a correlation compensation value for compensating the plurality of channels according to the at least one eigenvalue; a channel capacity computation unit, coupled to the eigenvalue computation unit and the channel compensation unit, for generating a channel capacity according to the at least one eigenvalue and the correlation compensation value; and a selection unit, coupled to the channel capacity computation unit, for determining a modulation and coding scheme (MCS) according to the channel capacity.
    Type: Application
    Filed: September 6, 2017
    Publication date: July 19, 2018
    Inventors: Chuan-Hu Lin, Chung-Yao Chang
  • Patent number: 9954647
    Abstract: The present invention discloses an ML (Maximum Likelihood) detector comprising: a search value selecting circuit selecting a first-layer search value; and an ML detecting circuit.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: April 24, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yao Chang, Chuan-Hu Lin, Yi-Syun Yang
  • Patent number: 9893841
    Abstract: The present invention discloses an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a first-layer search value. The ML detecting circuit is configured to carry out the following steps: selecting first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof, and adding one or more first-layer candidate value(s), if necessary; calculating second-layer candidate values according to all the above-mentioned first-layer candidate values, and adding one or more second-layer candidate value(s) and its/their corresponding first-layer candidate value(s), if necessary; and calculating log likelihood ratios according to the whole first-layer and second-layer candidate values.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 13, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chung-Yao Chang, Chuan-Hu Lin, Yi-Syun Yang
  • Publication number: 20170317787
    Abstract: The present invention discloses an ML (Maximum Likelihood) detector comprising: a search value selecting circuit selecting a first-layer search value; and an ML detecting circuit.
    Type: Application
    Filed: March 21, 2017
    Publication date: November 2, 2017
    Inventors: CHUNG-YAO CHANG, CHUAN-HU LIN, YI-SYUN YANG
  • Publication number: 20170317788
    Abstract: The present invention discloses an ML (Maximum Likelihood) detector. An embodiment of the ML detector comprises a search value selecting circuit and an ML detecting circuit. The search value selecting circuit is configured to select a first-layer search value. The ML detecting circuit is configured to carry out the following steps: selecting first-layer candidate values according to the first-layer search value, one of a reception signal and a derivative thereof, and one of a channel estimation signal and a derivative thereof, and adding one or more first-layer candidate value(s), if necessary; calculating second-layer candidate values according to all the above-mentioned first-layer candidate values, and adding one or more second-layer candidate value(s) and its/their corresponding first-layer candidate value(s), if necessary; and calculating log likelihood ratios according to the whole first-layer and second-layer candidate values.
    Type: Application
    Filed: March 21, 2017
    Publication date: November 2, 2017
    Inventors: CHUNG-YAO CHANG, CHUAN-HU LIN, YI-SYUN YANG
  • Patent number: 9749171
    Abstract: A communication receiving end for receiving an inputted signal includes a signal amplifier for adjusting the inputted signal according to a first predetermined gain or a second predetermined gain to generate a first adjusted signal; an analog-to-digital converter (ADC), coupled to the signal amplifier, for converting the first adjusted signal; and a control unit, coupled to the ADC, for determining whether the ADC is saturated or not according to an output of the ADC. The first predetermined gain is associated with a first inputted signal power processed by the communication receiving end and a quantization noise of the ADC. The second predetermined gain is associated with a second inputted signal power processed by the communication receiving end and a full scale level of the ADC. The first inputted signal power is smaller than the second inputted signal power.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: August 29, 2017
    Assignee: REALTEK SEMICONDUCTOR COTPORATION
    Inventors: Chung-Yao Chang, Chuan-Hu Lin
  • Publication number: 20170223668
    Abstract: A method of cell search for a mobile device in a wireless communication system is provided. The method comprises performing a reception timing detection procedure, to obtain at least a possible reception time for a primary synchronization signal (PSS), performing a PSS hypothesis procedure, to generate three frequency-domain PSS sequences according to three root indexes each corresponding to a physical layer identity, and performing a secondary synchronization signal (SSS) coherent detection procedure, to calculate a SSS sequence according to each of the at least a possible reception time with the three frequency-domain PSS sequences, to obtain a physical layer cell identity group corresponding to the SSS sequence.
    Type: Application
    Filed: September 19, 2016
    Publication date: August 3, 2017
    Inventors: Chung-Yao Chang, Chuan-Hu Lin
  • Publication number: 20170111204
    Abstract: A communication receiving end for receiving an inputted signal includes a signal amplifier for adjusting the inputted signal according to a first predetermined gain or a second predetermined gain to generate a first adjusted signal; an analog-to-digital converter (ADC), coupled to the signal amplifier, for converting the first adjusted signal; and a control unit, coupled to the ADC, for determining whether the ADC is saturated or not according to an output of the ADC. The first predetermined gain is associated with a first inputted signal power processed by the communication receiving end and a quantization noise of the ADC. The second predetermined gain is associated with a second inputted signal power processed by the communication receiving end and a full scale level of the ADC. The first inputted signal power is smaller than the second inputted signal power.
    Type: Application
    Filed: October 3, 2016
    Publication date: April 20, 2017
    Inventors: CHUNG-YAO CHANG, CHUAN-HU LIN