Patents by Inventor Chuan-Hua Chang
Chuan-Hua Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11281586Abstract: The invention provides a processor including a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets respectively corresponding to a plurality of cache sets of a cache memory in the cache system, each of the sets has a plurality of confidence values, and the prediction table provides the confidence values of a selected set according to the index. The prediction logic circuit receives the confidence values of the selected set, and generates a prediction result by judging whether each of the confidence values of the selected set is larger than a threshold value or not. The prediction verification circuit receives the prediction result, generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. Wherein, the prediction verification circuit updates the confidence values of the prediction table according to the update information.Type: GrantFiled: May 9, 2017Date of Patent: March 22, 2022Assignee: ANDES TECHNOLOGY CORPORATIONInventors: Kun-Ho Liu, Chieh-Jen Cheng, Chuan-Hua Chang, I-Cheng Kevin Chen
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Patent number: 11188468Abstract: A processor includes a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets, each of the sets has a hot way number, at least one warm way number, and at least one confidence value corresponding to the at least one warm way number. The prediction logic circuit generates a prediction result by predicting if the at least one warm way number is an opened way. The prediction verification circuit generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. The prediction verification circuit updates the hot way number, the at least one warm way number and the at least one confidence value of the at least one warm way number according to the update information.Type: GrantFiled: June 15, 2020Date of Patent: November 30, 2021Assignee: ANDES TECHNOLOGY CORPORATIONInventors: Kun-Ho Liu, Chieh-Jen Cheng, Chuan-Hua Chang, I-Cheng Kevin Chen
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Publication number: 20200310974Abstract: A processor includes a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets, each of the sets has a hot way number, at least one warm way number, and at least one confidence value corresponding to the at least one warm way number. The prediction logic circuit generates a prediction result by predicting if the at least one warm way number is an opened way. The prediction verification circuit generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. The prediction verification circuit updates the hot way number, the at least one warm way number and the at least one confidence value of the at least one warm way number according to the update information.Type: ApplicationFiled: June 15, 2020Publication date: October 1, 2020Applicant: ANDES TECHNOLOGY CORPORATIONInventors: Kun-Ho Liu, Chieh-Jen Cheng, Chuan-Hua Chang, I-Cheng Kevin Chen
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Patent number: 10579522Abstract: A method and a device for accessing a cache memory are provided. The method comprises: generating, by a bit prediction unit (BPU), a prediction bit corresponding to an instruction instructing to access the cache memory from a central processing unit (CPU); generating, by an instruction execution unit (IEU), a virtual address corresponding to the instruction; generating, by a load/store unit (LSU), a predicted cache index according to the prediction bit and a part of a virtual page offset of the virtual address; and reading, by the LSU, data from the cache memory by using the predicted cache index. Therefore, the maximum size of the cache memory could be increased.Type: GrantFiled: September 13, 2016Date of Patent: March 3, 2020Assignee: ANDES TECHNOLOGY CORPORATIONInventors: Chieh-Jen Cheng, Chuan-Hua Chang
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Publication number: 20180330259Abstract: The invention provides a processor including a prediction table, a prediction logic circuit, and a prediction verification circuit. The prediction table has a plurality of sets respectively corresponding to a plurality of cache sets of a cache memory in the cache system, each of the sets has a plurality of confidence values, and the prediction table provides the confidence values of a selected set according to the index. The prediction logic circuit receives the confidence values of the selected set, and generates a prediction result by judging whether each of the confidence values of the selected set is larger than a threshold value or not. The prediction verification circuit receives the prediction result, generates a correct/incorrect information according to the prediction result, and generates an update information according to the correct/incorrect information. Wherein, the prediction verification circuit updates the confidence values of the prediction table according to the update information.Type: ApplicationFiled: May 9, 2017Publication date: November 15, 2018Applicant: ANDES TECHNOLOGY CORPORATIONInventors: Kun-Ho Liu, Chieh-Jen Cheng, Chuan-Hua Chang, I-Cheng Kevin Chen
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Patent number: 10120688Abstract: A data processing system includes a control register, a program counter and a controller. The control register is used to store a level status of an execution flow and at least one return address. When the controller reads a block call instruction while a level status of the execution flow has an initial value, the controller stores a return address of the block call instruction in the control register, increments a value of the level status, and redirects the execution flow to a target address indicated by the block call instruction. When the controller reads a block return instruction and the value of the level status is not equal to the initial value, the controller decrements the value of the level status. If the value of the level status becomes equal to the initial value, the controller redirects the execution flow to the return address.Type: GrantFiled: November 15, 2016Date of Patent: November 6, 2018Assignee: Andes Technology CorporationInventors: Jen-Chih Tseng, Hong-Men Su, Chuan-Hua Chang
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Patent number: 10061940Abstract: A secure protection method executed by a processor is provided. The secure protection method includes the following steps: Perform a security checking before or after executing an instruction according to an instruction security attribute (ISA) of the instruction and a security attribute (SA) of an operational event (OE); and ignore the OE, defer the OE, or raise a security exception when the security checking fails. The OE is generated as a side effect when the processor fetches or executes the instruction, or generated as a monitoring result on the instruction, or generated in response to an external input of the processor.Type: GrantFiled: July 9, 2013Date of Patent: August 28, 2018Assignee: ANDES TECHNOLOGY CORPORATIONInventors: Chi-Chang Lai, Chuan-Hua Chang
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Publication number: 20180136934Abstract: A data processing system includes a control register, a program counter and a controller. The control register is used to store a level status of an execution flow and at least one return address. When the controller reads a block call instruction while a level status of the execution flow has an initial value, the controller stores a return address of the block call instruction in the control register, increments a value of the level status, and redirects the execution flow to a target address indicated by the block call instruction. When the controller reads a block return instruction and the value of the level status is not equal to the initial value, the controller decrements the value of the level status. If the value of the level status becomes equal to the initial value, the controller redirects the execution flow to the return address.Type: ApplicationFiled: November 15, 2016Publication date: May 17, 2018Inventors: Jen-Chih Tseng, Hong-Men Su, Chuan-Hua Chang
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Publication number: 20180074957Abstract: A method and a device for accessing a cache memory are provided. The method comprises: generating, by a bit prediction unit (BPU), a prediction bit corresponding to an instruction instructing to access the cache memory from a central processing unit (CPU); generating, by an instruction execution unit (IEU), a virtual address corresponding to the instruction; generating, by a load/store unit (LSU), a predicted cache index according to the prediction bit and a part of a virtual page offset of the virtual address; and reading, by the LSU, data from the cache memory by using the predicted cache index. Therefore, the maximum size of the cache memory could be increased.Type: ApplicationFiled: September 13, 2016Publication date: March 15, 2018Applicant: ANDES TECHNOLOGY CORPORATIONInventors: Chieh-Jen Cheng, Chuan-Hua Chang
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Patent number: 9899436Abstract: An image sensor includes a semiconductor substrate with at least one recess disposed on its surface and in the photosensitive area defined on the surface of the semiconductor substrate, a first-conductivity-type doped region disposed in the semiconductor substrate and in the photosensitive area, and a second-conductivity-type doped region disposed on the surface of the first-conductivity-type doped region and on the surface of the recess. A photosensitive device of the image sensor is formed of the first-conductivity-type doped region and the second-conductivity-type doped region.Type: GrantFiled: October 26, 2016Date of Patent: February 20, 2018Assignee: Powerchip Technology CorporationInventors: Shih-Ping Lee, Yu-An Chen, Hsiu-Wen Huang, Chuan-Hua Chang
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Publication number: 20180040651Abstract: An image sensor includes a semiconductor substrate with at least one recess disposed on its surface and in the photosensitive area defined on the surface of the semiconductor substrate, a first-conductivity-type doped region disposed in the semiconductor substrate and in the photosensitive area, and a second-conductivity-type doped region disposed on the surface of the first-conductivity-type doped region and on the surface of the recess. A photosensitive device of the image sensor is formed of the first-conductivity-type doped region and the second-conductivity-type doped region.Type: ApplicationFiled: October 26, 2016Publication date: February 8, 2018Inventors: Shih-Ping Lee, Yu-An Chen, Hsiu-Wen Huang, Chuan-Hua Chang
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Publication number: 20170012080Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including an isolation region and a device region is provided. An overall amorphization process is performed on the substrate to form an amorphous region. Here, a minimum depth of the amorphous region is greater than a maximum depth of at least one of the isolation region and the device region, and the amorphous region covers at least one of the isolation region and the device region. A thermal treatment is performed on the amorphous region.Type: ApplicationFiled: September 16, 2015Publication date: January 12, 2017Inventors: Shih-Ping Lee, Yu-An Chen, Hsiu-Wen Huang, Chuan-Hua Chang
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Publication number: 20150020211Abstract: A secure protection method executed by a processor is provided. The secure protection method includes the following steps. Perform a security checking before or after executing an instruction according to an instruction security attribute (ISA) of the instruction and a security attribute (SA) of an operational event (OE). Ignore the OE, defer the OE, or raise a security exception when the security checking fails. The OE is generated as a side effect when the processor fetches or executes the instruction, or generated as a monitoring result on the instruction, or generated in response to an external input of the processor.Type: ApplicationFiled: July 9, 2013Publication date: January 15, 2015Inventors: Chi-Chang Lai, Chuan-Hua Chang
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Publication number: 20130138921Abstract: A de-coupled co-processor interface (CPIF) is provided. The de-coupled CPIF transfers endian information along with the dispatching of co-processor (COP) instructions. The de-coupled CPIF divides the status report provided by a COP into an early status report and a late status report. The de-coupled CPIF may disable the late status report in order to improve the performance. The de-coupled CPIF further provides multiple early flush interfaces (EFIs) to transfer early flush events from a main processor (MP) to a corresponding COP. As a result, the de-coupled CPIF can improve the performance of the processing of data endian, status reports and early flush events between an MP and a COP.Type: ApplicationFiled: November 28, 2011Publication date: May 30, 2013Applicant: ANDES TECHNOLOGY CORPORATIONInventors: Yuan-Yuan Shih, Chuan-Hua Chang, Chi-Chang Lai
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Patent number: 8171188Abstract: To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.Type: GrantFiled: November 16, 2008Date of Patent: May 1, 2012Assignee: Andes Technology CorporationInventors: Chuan-Hua Chang, Hong-Men Su
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Patent number: 7934073Abstract: A method for performing a jump and translation state change procedure at the same time is disclosed. The method includes: carrying out a series of instruction processing in a first function in a first translation state; and executing a jump instruction which jumps to a target address in a second function and initiates and completes a translation state change to a second translation state at the same time; wherein an address of a next instruction after the jump instruction is stored as a return address in a first register.Type: GrantFiled: March 14, 2007Date of Patent: April 26, 2011Assignee: Andes Technology CorporationInventors: Chuan-Hua Chang, Hong-Men Su
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Patent number: 7822999Abstract: A computer system and a method for controlling a processor thereof are provided. A processor management unit (PMU) is programmed by the processor itself or by another processor according to a change of the operating condition of the processor. Then, a notification signal is sent to the PMU by the processor when the processor is entering a standby mode. Upon receiving the notification signal, the PMU adjusts the operating condition of the processor according to the change. Finally, a completion signal is sent by the PMU to the processor after the change of the operating condition of the processor is stabilized. Therefore, the unpredictable behavior caused by premature awakening of the processor during the adjustment of the operating condition can be avoided.Type: GrantFiled: June 4, 2007Date of Patent: October 26, 2010Assignee: Andes Technology CorporationInventors: Li-Hung Chang, Hong-Men Su, Chuan-Hua Chang
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Publication number: 20100211591Abstract: An exemplary string processing method for specific byte string processing with word-related instructions includes: loading a plurality of first predetermined strings; comparing a specific string with the loaded first predetermined strings simultaneously, thereby generating a plurality of comparison results corresponding to the specific string; and generating a string processing result according to the comparison results. A string processing apparatus uses the string processing method.Type: ApplicationFiled: February 16, 2009Publication date: August 19, 2010Inventors: Chuan-Hua Chang, Chi-Chang Lai, Hong-Men Su
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Publication number: 20100124308Abstract: To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream register when an underflow flag is set. The predetermined number equals a predetermined extraction width minus a previous starting position. The bits are stored in a lowest part of a destination register, and the underflow flag is cleared.Type: ApplicationFiled: November 16, 2008Publication date: May 20, 2010Inventors: Chuan-Hua Chang, Hong-Men Su
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Patent number: 7627743Abstract: A multi-word transfer instruction, a memory transfer method using the multi-word transfer instruction and a circuit implementation for transferring multiple words between a memory subsystem and a processor register file are provided. The multi-word transfer instruction specifies an access type (load or store), a consecutive register group, a selection mask and a base register for the starting address of the corresponding memory locations. Therefore, the total number of words accessed by this instruction is equal to the number of registers specified in the consecutive register group along with the number of the registers specified by the selection mask. Besides, additional information, such as an address update mode, an order mode and a modification mode, may be further specified in the multi-word transfer instruction.Type: GrantFiled: January 12, 2007Date of Patent: December 1, 2009Assignee: Andes Technology CorporationInventors: Hong-Men Su, Chuan-Hua Chang, Jen-Chih Tseng