Patents by Inventor Chuan-Jane Chao
Chuan-Jane Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9088252Abstract: A fixed voltage generating circuit includes a current mirror, a differential pair, and a resistor coupled to the current mirror. A node of the resistor is coupled to a voltage source. The differential pair includes two resistors coupled to the voltage source to enable the differential pair outputting a stable output voltage.Type: GrantFiled: March 5, 2014Date of Patent: July 21, 2015Assignee: RichWave Technology Corp.Inventors: Chih-Sheng Chen, Chuan-Jane Chao
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Patent number: 9052332Abstract: A pizeoresistive type Z-axis accelerometer is provided, including a substrate; a plurality of anchors formed over the substrate; a plurality of cantilever beams, wherein the cantilever beams include a piezoresistive material; and a proof mass, wherein the proof mass is suspended over the substrate by respectively connecting the proof mass with the anchors, and the accelerometer senses a movement of the proof mass by the piezoresistive material.Type: GrantFiled: May 31, 2012Date of Patent: June 9, 2015Assignee: RichWave Technology Corp.Inventors: Chih-Wei Huang, Chieh-Pin Chang, Ja-Hao Chen, Chuan-Jane Chao, Ying-Zong Juang, Shyh-Chyi Wong, Yeong-Her Wang
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Patent number: 8904868Abstract: A sensing apparatus includes an acceleration sensing unit, for measuring an acceleration applied to a proof mass, further including: a proof mass; a carrier signal source, for providing a carrier signal; a capacitive half-bridge, including a first and a second capacitor, wherein each capacitor is coupled to the proof mass and the carrier signal source, one with a positive electrode and the other one with a negative electrode, and the acceleration applied to the proof mass makes the carrier signal flow through the first and the second capacitor so that the first capacitor and the second capacitor respectively generates a first voltage and a second voltage variation which have opposite phases with each other; and an instrumentation amplifier, for receiving and amplifying the first voltage and the second voltage variation, whereby the magnitude and the direction of the acceleration applied to the proof mass is determined.Type: GrantFiled: April 27, 2012Date of Patent: December 9, 2014Assignee: RichWave Technology Corp.Inventors: Chih-Wei Huang, Chieh-Pin Chang, Ja-Hao Chen, Chuan-Jane Chao, Ying-Zong Juang, Shyh-Chyi Wong, Yeong-Her Wang
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Publication number: 20140253088Abstract: A fixed voltage generating circuit includes a current mirror, a differential pair, and a resistor coupled to the current mirror. A node of the resistor is coupled to a voltage source. The differential pair includes two resistors coupled to the voltage source to enable the differential pair outputting a stable output voltage.Type: ApplicationFiled: March 5, 2014Publication date: September 11, 2014Applicant: RichWave Technology Corp.Inventors: Chih-Sheng Chen, Chuan-Jane Chao
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Patent number: 8580627Abstract: A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.Type: GrantFiled: December 14, 2010Date of Patent: November 12, 2013Assignee: RichWave Technology Corp.Inventors: Kuo-Jui Peng, Chuan-Jane Chao, Tsyr-Shyang Liou
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Publication number: 20130091949Abstract: A pizeoresistive type Z-axis accelerometer is provided, including a substrate; a plurality of anchors formed over the substrate; a plurality of cantilever beams, wherein the cantilever beams include a piezoresistive material; and a proof mass, wherein the proof mass is suspended over the substrate by respectively connecting the proof mass with the anchors, and the accelerometer senses a movement of the proof mass by the piezoresistive material.Type: ApplicationFiled: May 31, 2012Publication date: April 18, 2013Applicant: RICHWAVE TECHNOLOGY CORP.Inventors: Chih-Wei HUANG, Chieh-Pin CHANG, Ja-Hao CHEN, Chuan-Jane CHAO, Ying-Zong JUANG, Shyh-Chyi WONG, Yeong-Her WANG
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Publication number: 20120285245Abstract: A sensing apparatus includes an acceleration sensing unit, for measuring an acceleration applied to a proof mass, further including: a proof mass; a carrier signal source, for providing a carrier signal; a capacitive half-bridge, including a first and a second capacitor, wherein each capacitor is coupled to the proof mass and the carrier signal source, one with a positive electrode and the other one with a negative electrode, and the acceleration applied to the proof mass makes the carrier signal flow through the first and the second capacitor so that the first capacitor and the second capacitor respectively generates a first voltage and a second voltage variation which have opposite phases with each other; and an instrumentation amplifier, for receiving and amplifying the first voltage and the second voltage variation, whereby the magnitude and the direction of the acceleration applied to the proof mass is determined.Type: ApplicationFiled: April 27, 2012Publication date: November 15, 2012Applicant: RICHWAVE TECHNOLOGY CORP.Inventors: Chih-Wei HUANG, Chieh-Pin CHANG, Ja-Hao CHEN, Chuan-Jane CHAO, Ying-Zong JUANG, Shyh-Chyi WONG, Yeong-Her WANG
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Publication number: 20110291226Abstract: A compound semiconductor device is provided, including a gallium arsenide (GaAs) substrate having a first protrusion portion and a second protrusion portion, wherein the first protrusion portion is formed over a first portion of the GaAs substrate and the second protrusion is formed over a second portion of the GaAs substrate. A first element is disposed over the first protrusion portion, and a second element is disposed over the second protrusion portion.Type: ApplicationFiled: December 14, 2010Publication date: December 1, 2011Applicant: RICHWAVE TECHNOLOGY CORP.Inventors: Kuo-Jui Peng, Chuan-Jane Chao, Tsyr-Shyang Liou
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Patent number: 8026767Abstract: An adaptive bias circuit which provides a more sensitive adaptive bias current with respect to power level is used for biasing an electronic circuit. The adaptive bias circuit has a first transistor coupled to a power supply, a voltage bias circuit coupled to the first transistor and the power supply biasing the first transistor, and a first power coupling module coupled to the first transistor and the electronic circuit for coupling a portion of input signal power to the first transistor. A second transistor is coupled to the first transistor and the power supply to increase the current gain of the adaptive bias circuit, and a second current coupling module is coupled to the second transistor and the electronic circuit to provide adaptive bias current to the electronic circuit.Type: GrantFiled: August 21, 2009Date of Patent: September 27, 2011Assignee: RichWave Technology Corp.Inventors: Chih-Wei Chen, Chuan-Jane Chao, Shyh-Chyi Wong
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Publication number: 20110043287Abstract: An adaptive bias circuit which provides a more sensitive adaptive bias current with respect to power level is used for biasing an electronic circuit. The adaptive bias circuit has a first transistor coupled to a power supply, a voltage bias circuit coupled to the first transistor and the power supply biasing the first transistor, and a first power coupling module coupled to the first transistor and the electronic circuit for coupling a portion of input signal power to the first transistor. A second transistor is coupled to the first transistor and the power supply to increase the current gain of the adaptive bias circuit, and a second current coupling module is coupled to the second transistor and the electronic circuit to provide adaptive bias current to the electronic circuit.Type: ApplicationFiled: August 21, 2009Publication date: February 24, 2011Inventors: Chih-Wei Chen, Chuan-Jane Chao, Shyh-Chyi Wong
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Patent number: 7692493Abstract: A high-efficiency single-to-differential amplifier has a first transistor acting as a first amplification stage. A second transistor, a third transistor, a first choke, a second choke, and a first capacitor form a second single-to-differential amplification stage. The first amplification stage receives and amplifies an input signal, outputs the amplified signal to the second single-to-differential amplification stage through a coupling module, and concurrently provides DC bias current to the second single-to-differential amplification stage through a tank. The second single-to-differential amplification stage reuses DC current of the first amplification stage, amplifies the output signal of the first amplification stage, and transfers it to a differential output.Type: GrantFiled: January 21, 2009Date of Patent: April 6, 2010Assignee: RichWave Technology Corp.Inventors: Chih-Wei Chen, Chuan-Jane Chao, Shyh-Chyi Wong
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Patent number: 7671704Abstract: An LC resonant circuit. The LC resonant circuit comprises an inductor and a conductor. The inductor is an electrode plate of a capacitor. The conductor is over, under, or on both sides of the inductor and used as the other electrode plate of the capacitor.Type: GrantFiled: June 26, 2007Date of Patent: March 2, 2010Assignee: Richwave Technology Corp.Inventors: Chia-Jen Hsu, Chuan-Jane Chao
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Publication number: 20080169883Abstract: An LC resonant circuit. The LC resonant circuit comprises an inductor and a conductor. The inductor is an electrode plate of a capacitor. The conductor is over, under, or on both sides of the inductor and used as the other electrode plate of the capacitor.Type: ApplicationFiled: June 26, 2007Publication date: July 17, 2008Inventors: Chia-Jen Hsu, Chuan-Jane Chao
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Patent number: 6870387Abstract: Measurement method and test structures for measuring interconnect coupling capacitance in an IC chip are provided. This method employs CBCM technique. In the first step, two test structures are used to measure a target configuration in order to obtain the total capacitance C of a metal line with respect to ground including line-to-line, fringe and area components (C=2Cc+2Cf+Ca). In the second step, two other test structures are used to measure a dummy configuration in order to obtain the area and fringe capacitance Cdummy of the metal line with respect to ground including fringe and area components (Cdummy=2Cf+Ca). After the two steps, the coupling capacitance Cc between the metal line and another line can be determined according to the formula Cc=(C?Cdummy)/2.Type: GrantFiled: November 4, 2003Date of Patent: March 22, 2005Assignee: Winbond Electronics CorporationInventors: Kai-Ye Huang, Chuan-Jane Chao
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Patent number: 6858900Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.Type: GrantFiled: October 8, 2001Date of Patent: February 22, 2005Assignee: Winbond Electronics CorpInventors: Wei-Fan Chen, Shi-Tron Lin, Chuan-Jane Chao
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Publication number: 20050024077Abstract: Measurement method and test structures for measuring interconnect coupling capacitance in an IC chip are provided. This method employs CBCM technique. In the first step, two test structures are used to measure a target configuration in order to obtain the total capacitance C of a metal line with respect to ground including line-to-line, fringe and area components(C=2Cc+2Cf+Ca). In the second step, two other test structures are used to measure a dummy configuration in order to obtain the area and fringe capacitance Cdummy of the metal line with respect to ground including fringe and area components (Cdummy=2Cf+Ca). After the two steps, the coupling capacitance Cc between the metal line and another line can be determined according to the formula Cc=(C-Cdummy)/2.Type: ApplicationFiled: November 4, 2003Publication date: February 3, 2005Inventors: Kai-Ye Huang, Chuan-Jane Chao
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Publication number: 20030067040Abstract: ESD protection devices and methods of forming them are provided in this invention. By employing the thin gate oxide fabricated by a dual gate oxide process and breakdown-enhanced layers, ESD protection devices with a lower trigger voltage are provided. The NMOS structure for ESD protection according to the present invention has islands, a control gate and breakdown-enhanced layers. These islands as well as the breakdown-enhanced layers overlapping the drain region of the NMOS reduce the breakdown voltage of the PN junction in the drain region, thereby reducing the ESD trigger voltage and improving the ESD protection level of the NMOS. Furthermore, the invention is applicable to general integrated-circuit processes as well as various ESD protection devices.Type: ApplicationFiled: October 8, 2001Publication date: April 10, 2003Applicant: Winbond Electronics Corp.Inventors: Wei-Fan Chen, Shi-Tron Lin, Chuan-Jane Chao
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Patent number: 6541325Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.Type: GrantFiled: May 1, 2002Date of Patent: April 1, 2003Assignee: Windbond Electronics CorporationInventors: Chih-Mu Huang, Chuan-Jane Chao, Chi-Hung Kao
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Publication number: 20020123191Abstract: The present invention discloses a simple and convenient method for fabricating a capacitor device with BiCMOS processes. An electrode of the capacitor device formed according to the present invention is an ion doping region formed in an epitaxy layer so that the thickness of the dielectric layer of the capacitor device decreased relative to a specific ion concentration. Accordingly, the capacitor device formed therein has a high capacitance and good performance.Type: ApplicationFiled: May 1, 2002Publication date: September 5, 2002Applicant: Winbond Electronics Corporation, a Taiwan corporationInventors: Chih-Mu Huang, Chuan-Jane Chao, Chi-Hung Kao
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Publication number: 20020118035Abstract: A method for measuring both buried strap and deep trench leakage currents in DRAM cell capacitors. By keeping the voltages on both plates of the capacitor equal, the buried strap leakage current (IBS) may be isolated and measured. A range of voltages is applied to a terminal of an associated transistor to obtain a corresponding range of buried strap leakage currents. An unequal voltage is next applied across the capacitor, and a total leakage current is measured. By applying a known potential to a substrate of the transistor during this total leakage current measurement, the associated IBS may be determined. Next, the IBS is subtracted from the measured total leakage current to obtain the deep trench leakage current (IDT).Type: ApplicationFiled: March 1, 2002Publication date: August 29, 2002Applicant: Winbond Electronics Corporation (Taiwan)Inventors: Shih-Hsien Yang, Chuan-Jane Chao