Abstract: A memory device includes a memory array, a multiply-accumulate (MAC) circuit and an encoder-decoder circuit. The MAC circuit performs a MAC operation on an encoded weight data stored in the memory array and an input data to generate a partial MAC result. An encoder of the encoder-decoder circuit is configured to encode m weight bits among n weight bits of weight data according to an encryption key to generate the encoded weight data, wherein m and n are positive integers, and m is less than n. A decoder of the encoder-decoder circuit is configured to detect an error in the partial MAC result according to the encryption key to generate a decoded partial MAC result.

Abstract: A computing circuit is provided. The computing circuit is disposed in a memory device and electrically coupled to a memory cell of the memory device. The computing circuit includes a weight decoder, a multiplier, an adder tree, and an accumulator. The weight decoder is configured to obtain a compressed weight from the memory cell and generate a decoded weight based on the compressed weight. The multiplier is configured to generate a partial-product by multiplying an input signal with the decoded weight. The adder tree is configured to generate a partial-sum by performing an addition operation based on the partial-product. The accumulator is configured to generate an accumulated sum by performing an accumulation operation based on the partial-sum and output an output signal based on the accumulated sum. The accumulated sum is left shifted based on a shift signal.

Abstract: A memory structure with input-aware maximum multiply-and-accumulate value zone prediction for computing-in-memory applications includes a memory array, an input-aware zone prediction circuit and an analog-to-digital converter. An input-aware maximum partial multiply-and-accumulate value voltage generator is configured to generate a maximum partial multiply-and-accumulate value according to at least one input value. A prediction-aware global reference voltage generator is configured to generate a plurality of global reference voltages, a maximum reference voltage and a selected minimum reference voltage. A maximum partial multiply-and-accumulate value zone detector is configured to generate a zone switch signal by comparing the maximum partial multiply-and-accumulate value and the global reference voltages.