Patents by Inventor Chuan-Kai Lo

Chuan-Kai Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6559049
    Abstract: The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: May 6, 2003
    Assignee: Lam Research Corporation
    Inventors: Lawrence Chen, Chang-Tai Chiao, Young Tong Tsai, Francis Ko, Chuan-Kai Lo
  • Publication number: 20030032278
    Abstract: The present invention reveals a semiconductor dual damascene etching process, which uses a confined plasma etching chamber to integrate all dual damascene steps such as via hole etching, photoresist stripping and barrier layer removal which originally performed in various reactors as a continuous procedure in the confined plasma chamber. The confined plasma chamber including a confinement ring surrounding a wafer and an anti-etching upper electrode plate performs the steps mentioned above under clean mode. The present invention can not only reduce the time period required by the semiconductor dual damascene process but also greatly reduce the manufacturing cost.
    Type: Application
    Filed: July 31, 2002
    Publication date: February 13, 2003
    Applicant: Lam Research Corporation
    Inventors: Lawrence Chen, C.T. Chiao, Young Tong Tsai, Francis Ko, Chuan-Kai Lo
  • Patent number: 6486070
    Abstract: An etch that provides a high oxide to photoresist selectivity in a low-pressure, high-density plasma is provided. An extremely high reverse RIE lag is achieved, wherein the etching of small high-aspect ratio openings is possible, but that of large openings is not. A high-density plasma is generated so that carbon monoxide (CO) is ionized to CO+ so that at least 1 sccm equivalent of CO+ is provided. Excited CO neutrals (CO*) are also present within the plasma. Fluorocarbon and hydrofluorocarbon gases are also provided. The excited CO neutrals scavenge free fluorine, near the wafer surface and in the large openings, increasing polymer deposition on the photoresist and in the large openings thus reduce or stop etching in those regions.
    Type: Grant
    Filed: September 21, 2000
    Date of Patent: November 26, 2002
    Assignee: Lam Research Corporation
    Inventors: Chok W. Ho, Fang-Ju Lin, Chuan-Kai Lo