Patents by Inventor Chuan Khye Chai
Chuan Khye Chai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9128501Abstract: An integrated circuit having a regulator circuit capable of tracking reference voltages is provided. The integrated circuit includes shunt regulator circuitry. The shunt regulator circuitry includes a shunt regulator circuit and a voltage tracking circuit. The shunt regulator circuit has an output on which a regulated voltage is provided. The shunt regulator circuit also provides electrical current to the output when the regulated voltage is outside of a voltage range bounded by first and second reference voltages. The voltage tracking circuit may be coupled to the shunt regulator circuit. The voltage tracking circuit may generate the first and second reference voltages. In one instance, the first voltage is greater than the regulated voltage and the second voltage is less than the regulated voltage.Type: GrantFiled: September 11, 2013Date of Patent: September 8, 2015Assignee: Altera CorporationInventors: Kok Siang Tan, Chuan Khye Chai, Wilfred Wee Kee King
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Patent number: 9112646Abstract: One embodiment relates to an interpolator-based clock and data recovery (iCDR) circuit. The iCDR circuit includes an automatic gain control circuit arranged to generate an interpolation jump size signal when a targeted sampling detection signal is asserted. The targeted sampling detection signal may be asserted when sampling by the phase detector of the iCDR circuit is within a targeted range. The interpolation jump size signal may indicate a number of phase steps to shift an interpolation state signal if a jump is indicated by a filtered feedback signal. Other embodiments and features are also disclosed.Type: GrantFiled: February 11, 2014Date of Patent: August 18, 2015Assignee: Altera CorporationInventors: Chuan Thim Khor, Chuan Khye Chai
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Publication number: 20150070086Abstract: An integrated circuit having a regulator circuit capable of tracking reference voltages is provided. The integrated circuit includes shunt regulator circuitry. The shunt regulator circuitry includes a shunt regulator circuit and a voltage tracking circuit. The shunt regulator circuit has an output on which a regulated voltage is provided. The shunt regulator circuit also provides electrical current to the output when the regulated voltage is outside of a voltage range bounded by first and second reference voltages. The voltage tracking circuit may be coupled to the shunt regulator circuit. The voltage tracking circuit may generate the first and second reference voltages. In one instance, the first voltage is greater than the regulated voltage and the second voltage is less than the regulated voltage.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: Altera CorporationInventors: Kok Siang Tan, Chuan Khye Chai, Wilfred Wee Kee King
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Patent number: 8687755Abstract: One embodiment relates to an interpolator-based clock and data recovery (iCDR) circuit. The iCDR circuit includes an automatic gain control circuit arranged to generate an interpolation jump size signal when a targeted sampling detection signal is asserted. The targeted sampling detection signal may be asserted when sampling by the phase detector of the iCDR circuit is within a targeted range. The interpolation jump size signal may indicate a number of phase steps to shift an interpolation state signal if a jump is indicated by a filtered feedback signal. Other embodiments and features are also disclosed.Type: GrantFiled: January 31, 2012Date of Patent: April 1, 2014Assignee: Altera CorporationInventors: Chuan Thim Khor, Chuan Khye Chai
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Patent number: 8687738Abstract: A clock data recovery circuit includes a phase detector circuit, a majority voter circuit, and a phase shift circuit. The phase detector circuit is operable to compare a phase of a periodic signal to a phase of a data signal to generate a phase error signal. The majority voter circuit includes a shift register circuit. The shift register circuit is operable to generate an output signal based on the phase error signal. The majority voter circuit is operable to generate a majority vote of the phase error signal based on the output signal of the shift register circuit. The phase shift circuit is operable to set the phase of the periodic signal based on the majority vote generated by the majority voter circuit.Type: GrantFiled: April 1, 2011Date of Patent: April 1, 2014Assignee: Altera CorporationInventors: Swee Wah Lee, Teng Chow Ooi, Chuan Khye Chai
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Patent number: 8253448Abstract: A circuit includes first and second frequency divider circuits and first storage circuits. Each of the first and the second frequency divider circuits receives periodic input signals and generates a periodic output signal having a frequency of one of the periodic input signals in a bypass mode. The periodic output signal of each of the first and the second frequency divider circuits has a fraction of a frequency of one of the periodic input signals in a frequency divider mode. Each of the first storage circuits stores an enable signal in response to the periodic output signal of one of the first frequency divider circuits. The enable signals stored in the first storage circuits enable the second frequency divider circuits in the frequency divider mode. The circuit may include second storage circuits storing enable signals that enable a subset of the first frequency divider circuits in the frequency divider mode.Type: GrantFiled: July 19, 2010Date of Patent: August 28, 2012Assignee: Altera CorporationInventors: Chuan Thim Khor, Chuan Khye Chai, Edwin Yew Fatt Kok
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Patent number: 8189362Abstract: Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.Type: GrantFiled: June 1, 2011Date of Patent: May 29, 2012Assignee: Altera CorporationInventors: Jun Pin Tan, Tze Swan Tan, Chuan Khye Chai, Boon Jin Ang, Kar Keng Chua
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Patent number: 8120407Abstract: A circuit includes a phase detection circuit and a phase change circuit. The phase detection circuit compares a phase of a first periodic signal to an input signal to generate a gain signal. The phase change circuit provides phase shifts to the first periodic signal in first and second directions when the gain signal has a first value. The phase change circuit increases phase shifts provided to the first periodic signal in the first direction in response to the gain signal changing from the first value to a second value. The phase change circuit provides phase shifts to the first periodic signal in the second direction when the gain signal has the second value that are smaller than the phase shifts provided to the first periodic signal in the first direction when the gain signal has the second value.Type: GrantFiled: December 18, 2009Date of Patent: February 21, 2012Assignee: Altera CorporationInventors: Teng Chow Ooi, Eng Huat Lee, Chuan Khye Chai, Yew Fatt (Edwin) Kok, Sergey Shumarayev
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Publication number: 20110292711Abstract: Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.Type: ApplicationFiled: June 1, 2011Publication date: December 1, 2011Inventors: Jun Pin Tan, Tze Swan Tan, Chuan Khye Chai, Boon Jin Ang, Kar Keng Chua
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Patent number: 7978493Abstract: Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.Type: GrantFiled: September 18, 2008Date of Patent: July 12, 2011Assignee: Altera CorporationInventors: Jun Pin Tan, Tze Swan Tan, Chuan Khye Chai, Boon Jin Ang, Kar Keng Chua