Patents by Inventor Chuan-Lan Lin

Chuan-Lan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250239463
    Abstract: A method for fabricating a semiconductor device includes the steps of defining a scribe line on a front side of a wafer, forming an inter-metal dielectric (IMD) layer on the wafer, forming an alternating stack on the IMD layer, removing the alternating stack to form a trench, forming a passivation layer extending from the alternating stack to the trench, and then performing a dicing process along the scribe line to dice the passivation layer and the wafer.
    Type: Application
    Filed: February 25, 2024
    Publication date: July 24, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ting Lin, Chuan-Lan Lin, Yu-Ping Wang, Chu-Fu Lin
  • Publication number: 20250218902
    Abstract: A semiconductor structure includes a bottom wafer having a bottom substrate and a bottom interconnect structure on the bottom substrate, and a top wafer having a top substrate with a front surface and a rear surface and a top interconnect structure disposed on the front surface of the top substrate. The top interconnect structure is directly bonded to the bottom interconnect structure of the bottom wafer. An oxide-nitride-oxide (ONO) dielectric layer covers the rear surface of the top substrate. A plurality of conductive vias is disposed on the rear surface and extending into the ONO dielectric layer and the top substrate.
    Type: Application
    Filed: January 26, 2024
    Publication date: July 3, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chu-Fu Lin, Chuan-Lan Lin, Yu-Ping Wang, Chun-Hung Chen
  • Publication number: 20250166997
    Abstract: The invention provide an edge structure of a semiconductor wafer, which comprise a first substrate, an edge region and a device region are defined on that first substrate, a first material layer covers a first surface and a side surface of the edge region, and a second material layer covers the first material layer, the cross-sectional structure of the second material layer gradually decreases from the device region to the edge region.
    Type: Application
    Filed: December 13, 2023
    Publication date: May 22, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ping Wang, Chuan-Lan Lin, Chu-Fu Lin, Teng-Chuan Hu, Kun-Ju Li
  • Publication number: 20250015023
    Abstract: The invention provides a semiconductor structure, which comprises a plurality of metal circuit layers stacked with each other, the multi-layer metal circuit layer comprises an aluminum circuit layer which is located at the position closest to a surface among the plurality of circuit layers, the material of the aluminum circuit layer is made of aluminum, and the aluminum circuit layer comprises a concave portion.
    Type: Application
    Filed: August 2, 2023
    Publication date: January 9, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chiu-Jung Chiu, Chung-Hsing Kuo, Chun-Ting Yeh, Chuan-Lan Lin, Yu-Ping Wang, Yu-Chun Chen
  • Publication number: 20240429093
    Abstract: A method for fabricating a semiconductor device includes the steps of first defining a scribe line on a front side of a wafer, in which the wafer includes an inter-metal dielectric (IMD) layer disposed on a substrate and an alternating stack disposed on the IMD layer. Next, part of the alternating stack is removed to form a trench on the front side of the wafer, a dielectric layer is formed in the trench, and then a dicing process is performed along the scribe line from a back side of the wafer to divide the wafer into chips.
    Type: Application
    Filed: July 21, 2023
    Publication date: December 26, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ting Lin, Kai-Kuang Ho, Chuan-Lan Lin, Yu-Ping Wang, Chu-Fu Lin, Yi-Feng Hsu, Yu-Jie Lin
  • Publication number: 20240371695
    Abstract: A method for fabricating a semiconductor device includes the steps of first providing a wafer, forming a scribe line on a front side of the wafer, performing a plasma dicing process to dice the wafer along the scribe line without separating the wafer completely, performing a laminating process to form a tape on the front side of the wafer, performing a grinding process on a backside of the wafer, and then performing an expanding process to divide the wafer into chips.
    Type: Application
    Filed: June 1, 2023
    Publication date: November 7, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo
  • Publication number: 20240315095
    Abstract: A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.
    Type: Application
    Filed: April 18, 2023
    Publication date: September 19, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chu-Fu Lin, Chun-Ting Yeh, Chung-Hsing Kuo, Yi-Feng Hsu
  • Publication number: 20240162401
    Abstract: A method for fabricating a micro display device includes the steps of providing a wafer comprising a first area, a second area, and a third area, forming first bonding pads on the first area, forming second bonding pads on the second area, and forming third bonding pads on the third area. Preferably, the first bonding pads and the second bonding pads are made of different materials and the first bonding pads and the third bonding pads are made of different materials.
    Type: Application
    Filed: December 9, 2022
    Publication date: May 16, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chuan-Lan Lin, Yu-Ping Wang, Chien-Ting Lin, Chun-Ting Yeh