Patents by Inventor Chuan-Lin HSIAO
Chuan-Lin HSIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240420992Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.Type: ApplicationFiled: August 26, 2024Publication date: December 19, 2024Inventors: Chuan-Lin HSIAO, Wei-Ming LIAO
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Publication number: 20240365530Abstract: A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric conformally formed on the first groove and the first slot.Type: ApplicationFiled: July 5, 2024Publication date: October 31, 2024Inventors: Tseng-Fu LU, Chuan-Lin HSIAO
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Patent number: 12107002Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.Type: GrantFiled: October 11, 2023Date of Patent: October 1, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chuan-Lin Hsiao, Wei-Ming Liao
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Patent number: 12063771Abstract: A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric confomally formed on the first groove and the first slot.Type: GrantFiled: February 15, 2022Date of Patent: August 13, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Tseng-Fu Lu, Chuan-Lin Hsiao
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Patent number: 11935780Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.Type: GrantFiled: November 11, 2021Date of Patent: March 19, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Chuan-Lin Hsiao, Wei-Ming Liao
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Publication number: 20240047265Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.Type: ApplicationFiled: October 11, 2023Publication date: February 8, 2024Inventors: Chuan-Lin HSIAO, Wei-Ming LIAO
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Patent number: 11895830Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.Type: GrantFiled: December 3, 2021Date of Patent: February 6, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chuan-Lin Hsiao
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Patent number: 11832432Abstract: The present application provides a method of manufacturing a memory device having several word lines (WL) with reduced leakage. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation surrounding the active area; forming a first recess extending into the semiconductor substrate and across the active area; forming a first lining portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first lining portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer enclosing the first conductive member; and forming a first protruding portion of the first insulating layer above the first conductive layer and the first conductive member.Type: GrantFiled: December 16, 2021Date of Patent: November 28, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chuan-Lin Hsiao
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Publication number: 20230262958Abstract: A memory structure includes a substrate, a first word line and a first word line. The substrate has a plurality of active areas and an isolation structure surrounding the active areas. The first word line trench is formed across a first active area of the active areas and the isolation structure. The first word line trench includes a first slot and a first groove. The first slot is recessed from a top surface of the substrate. The first groove expands from a bottom of the first slot. A first sidewall is connected between the bottom of the first slot and a top of the first groove. A first word line is formed in the first word line trench. The first word line comprises a gate dielectric confomally formed on the first groove and the first slot.Type: ApplicationFiled: February 15, 2022Publication date: August 17, 2023Inventors: Tseng-Fu LU, Chuan-Lin HSIAO
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Patent number: 11688783Abstract: The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.Type: GrantFiled: December 7, 2021Date of Patent: June 27, 2023Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chuan-Lin Hsiao
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Publication number: 20230197771Abstract: The present application provides a memory device having several word lines (WL) with reduced leakage and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with an active area and including a recess extending into the semiconductor substrate; and a word line disposed within the recess, wherein the word line includes an insulating layer disposed within the recess, a conductive layer surrounded by the insulating layer, and a conductive member enclosed by the conductive layer, and the insulating layer includes a lining portion conformal to the recess and a protruding portion disposed above the conductive layer. A method of manufacturing the memory device is also disclosed.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Inventor: Chuan-Lin HSIAO
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Publication number: 20230200044Abstract: The present application provides a method of manufacturing a memory device having several word lines (WL) with reduced leakage. The method includes steps of providing a semiconductor substrate defined with an active area and including an isolation surrounding the active area; forming a first recess extending into the semiconductor substrate and across the active area; forming a first lining portion of a first insulating layer conformal to the first recess; disposing a first conductive material conformal to the first lining portion; forming a first conductive member surrounded by the first conductive material; disposing a second conductive material over the first conductive member to form a first conductive layer enclosing the first conductive member; and forming a first protruding portion of the first insulating layer above the first conductive layer and the first conductive member.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Inventor: CHUAN-LIN HSIAO
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Publication number: 20230180466Abstract: The present disclosure provides a method for manufacturing a semiconductor device having a buried wordline. The method includes forming a first recessed portion in a first dielectric layer in a substrate; forming a second recessed portion spaced apart from the first recessed portion and in the substrate; disposing a protection layer on the substrate to cover the second recessed portion; and disposing a second dielectric layer on the first dielectric layer.Type: ApplicationFiled: December 3, 2021Publication date: June 8, 2023Inventor: CHUAN-LIN HSIAO
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Publication number: 20230178614Abstract: The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.Type: ApplicationFiled: December 7, 2021Publication date: June 8, 2023Inventor: Chuan-Lin HSIAO
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Publication number: 20230141995Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.Type: ApplicationFiled: November 11, 2021Publication date: May 11, 2023Inventors: Chuan-Lin HSIAO, Wei-Ming LIAO