Abstract: A stamping assembly includes an upper die, a lower die, first pins and second pins. Each of the upper and lower dies has columns of depressions and columns of guiding holes. Each column of the guiding holes is disposed between two adjacent columns of the depressions. The depressions of one of the upper and lower dies are registered with the guiding holes of another one of the upper and lower dies. The first pins and second pins are respectively positioned in the guiding holes of the upper and lower dies and extend outwardly. The first pins and the second pins are respectively arranged into first and second matrices.

Abstract: An LED driver, an LED lighting system and an operating method thereof are provided. The LED driver is for driving an LED light source and includes a strobe circuit and a DC-DC converter. The strobe circuit generates a low-frequency modulation signal. The DC-DC converter is coupled to the strobe circuit and is configured to provide an adjustable operating current to the LED light source according to a DC signal and the low-frequency modulation signal. The operating current includes a DC current signal and a low-frequency AC current signal corresponding to the DC signal and the low-frequency modulation signal respectively. A frequency of the low-frequency AC current signal is between 25 Hz and 100 Hz, and a current ripple factor, equaling a difference of a maximum value and a minimum value of the operating current divided by a sum of the maximum value and the minimum value, is less than 8%.

Abstract: A bilayer controlled-release oral formulation comprises a first composition as an immediate release layer, and a second composition as a controlled-release layer. The first composition includes a xanthine derivative. The second composition includes a xanthine derivative and an enteric excipient. The in vitro dissolution of the second composition releases less than 35% by weight of the xanthine derivative in the second composition within 90 minutes, and the in vitro dissolution of the second composition releases 50% by weight or more of the xanthine derivative in the second composition within 3 hours.

Abstract: An integrated circuit in a transmitter includes a multi-lane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi-lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively. (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier.

Abstract: An LED power supply is provided. The LED power supply adopts constant-voltage/constant-current control, supplies power to an LED device, and includes an isolated DC-DC conversion circuit having primary and secondary sides and a control module. The control module includes a control unit, a feedback circuit, first and second switches and an optocoupler. The control unit is electrically connected to the primary side and controls operation of the conversion circuit. The optocoupler is configured for signal transmission with electrical isolation and includes a transmitter and a receiver electrically connected to the secondary side and the control unit respectively. When the output voltage is lower than a threshold voltage, the first switch is turned off, the second switch is turned on to trigger the optocoupler to generate a trigger signal at the receiver, and the control unit controls the isolated DC-DC conversion circuit to stop operating based on the trigger signal.

Abstract: A glitch-free clock switching circuit with clock loss tolerance and an operation method thereof and a corresponding glitch-free clock switching device are provided. The glitch-free clock switching circuit includes a first and a second stuck-status detection circuits, a first and a second reset synchronizers and a glitch-free switching core circuit. The glitch-free switching core circuit performs clock switching according to a clock switching signal to switch an output clock of the glitch-free clock switching circuit from an original clock source to a target clock source, where the original clock source and the target clock source represent one and the other of a first clock source and a second clock source, respectively; wherein the glitch-free clock switching circuit performs the clock switching based on a first synchronized reset signal and a second synchronized reset signal to provide the clock loss tolerance.

Abstract: A method for preparing a modular planar interconnect plate for a solid oxide fuel cell includes the steps of: (a) providing a metal blank sheet that includes a main region and a circumferential region; (b) stamping the metal blank sheet to simultaneously form columns of upper protrusions on an upper surface of the main region, columns of lower depressions on a lower surface of the main region, and a front upper retaining protrusion unit and a rear upper retaining protrusion unit on a right side area and a left side area of the circumferential region; (c) stamping the main region to form rows of lower protrusions on the lower surface of the main region and rows of upper depressions on the upper surface of the main region; and (d) forming a pair of upper elongation plates respectively and detachably retained between the front and rear upper retaining protrusion units.

Abstract: A buck converter using an ultra-low working current is provided. An error amplifier amplifies a difference between a voltage of an output terminal of the buck converter and a reference voltage to output an error amplified signal. A comparator compares a voltage of the error amplified signal with a ramp voltage to output a comparison signal. A control circuit controls a driver circuit to drive a high-side switch and a low-side switch according to the comparison signal. When the buck converter does not enter an ultra-low current mode, a low current controller circuit controls a system circuit to obtain an input current from an input power source. When the buck converter enters the ultra-low current mode, the low current controller circuit controls the system circuit to stop obtaining the input current from the input power source.

Abstract: A LED power supply with bi-level dimming receives an input voltage to supply power to an LED lamp, and adjusts the brightness of the LED lamp according to whether an external detection switch is triggered to be turned on. The LED power supply includes a conversion circuit, a switch, and an oscillation circuit. The conversion circuit converts the input voltage into an output voltage, and provides the output voltage to supply power to the LED lamp so as to control the LED lamp to provide a first brightness. The oscillation circuit provides a dimming signal with a fixed frequency and a duty cycle to the switch when the external detection switch is turned on so as to turn on and turn off the switch. The switch correspondingly adjusts the output voltage according to the dimming signal to control the LED lamp to provide a second brightness.

Abstract: A bi-level dimming LED power supply equipment adjusts the brightness of a plurality of LED lights according to whether an external detection switch is triggered turned on. The LED power supply equipment includes a plurality of LED power supplies, and the LED power supplies respectively include an input end and an output end. The input end receives an input voltage, and the output end includes a bus positive end, a bus negative end and a dimming end. The dimming end is commonly coupled to a first end of the external detection switch, and one of the bus positive end or the bus negative end is commonly coupled to a second end of the external detection switch and one end of the LED lights, and the other one of the bus positive end or the bus negative end is respectively coupled to the other ends of the LED lights.

Abstract: A LED power supply with bi-level dimming receives an input voltage to supply power to an LED lamp, and adjusts the brightness of the LED lamp according to whether an external detection switch is triggered to be turned on. The LED power supply includes a conversion circuit, a switch, and an oscillation circuit. The conversion circuit converts the input voltage into an output voltage, and provides the output voltage to supply power to the LED lamp so as to control the LED lamp to provide a first brightness. The oscillation circuit provides a dimming signal with a fixed frequency and a duty cycle to the switch when the external detection switch is turned on so as to turn on and turn off the switch. The switch correspondingly adjusts the output voltage according to the dimming signal to control the LED lamp to provide a second brightness.

Abstract: A foreign object detecting system and a method are provided. A control circuit controls a light transmitter and a light receiver. The light transmitter is disposed adjacent to a detected object and emits a light signal toward the detected object. The light receiver is disposed adjacent to the detected object in a path along which the light signal reflected by the detected object travels. The light receiver receives the light signal reflected to the light receiver. In a pre-operation, the control circuit defines the light signal received by the light receiver when the foreign object is not on the detected object as a first reflected light signal. In a detection operation, the control circuit determines that a difference exists between the light signal currently received by the light receiver and the first reflected light signal, the control circuit determines that the foreign object is on the detected object.

Abstract: Systems and methods are provided. A physical measurement of the core loss increase associated with a physical deformation of a material of the device is obtained. A data structure describing a model of the device is accessed. A first edge of the model of the device associated with a physical deformation of the device is identified. A finite element mesh is generated to include a single layer mesh comprising a plurality of mesh elements associated with the first edge of the finite element mesh. A core loss value is assigned to each of the plurality of mesh elements. Each of the core loss values representative of the physical measurement of the core loss increase of the material as a result of the physical deformation of the material. An electromagnetic model is generated by performing a finite element analysis based on the finite element mesh and the single layer mesh.

Abstract: A glitch-free clock switching circuit with clock loss tolerance and an operation method thereof and a corresponding glitch-free clock switching device are provided. The glitch-free clock switching circuit includes a first and a second stuck-status detection circuits, a first and a second reset synchronizers and a glitch-free switching core circuit. The glitch-free switching core circuit performs clock switching according to a clock switching signal to switch an output clock of the glitch-free clock switching circuit from an original clock source to a target clock source, where the original clock source and the target clock source represent one and the other of a first clock source and a second clock source, respectively; wherein the glitch-free clock switching circuit performs the clock switching based on a first synchronized reset signal and a second synchronized reset signal to provide the clock loss tolerance.

Abstract: An integrated circuit in a transmitter includes a multi-lane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi-lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively. (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier.

Abstract: A control method for an LLC resonant converter includes the following steps. Firstly, the LLC resonant converter is enabled. Then, the sonant converter is operated in a first modulation mode, so that the magnitude of the output voltage is greater than or equal to an intermediate voltage value. When the magnitude of the output current is greater than zero, a determining step is performed to determine whether the magnitude of the output voltage is greater than a reference voltage value. When the determining result is satisfied, the LLC resonant converter is operated in the first modulation mode. When the determining result is not satisfied, the LLC resonant converter is operated in a second modulation mode, so that the magnitude of the output voltage is lower than the intermediate voltage value.

Abstract: An integrated circuit in a transmitter includes a multi-lane interface, N signal generating circuits, a lane selection circuit and a control circuit. The multi-lane interface has N lanes. M of the N signal generating circuits are configured to generate M clock signals respectively. (N-M) of the N signal generating circuits are configured to generate (N-M) data signals respectively. The lane selection circuit is configured to select M of the N lanes as M clock lanes by coupling the M clock signals to the M clock lanes respectively, and couple one of the (N-M) data signals to one of remaining (N-M) lanes, serving as (N-M) data lanes, according to a data select signal. The control circuit is configured to generate a data select signal according to a lane identifier of the one of the (N-M) lanes. The data select signal has a signal value mapping to the lane identifier.

Abstract: Data is received that comprises a full model for a physical object having a rotating part and a stationary part. The physical object includes fields coupled between the rotating part and the stationary part. A mesh is then generated for a portion of the physical object that includes a rotating mesh and a stationary mesh. Thereafter, a partial simulation model is created based on the full model and the mesh. Coupling relationships are established for the fields between the rotating mesh and the stationary mesh in the partial simulation model. The fields are then solved based on the coupling relationship of the partial simulation model. Thereafter, fields of the full model can be recovered based on the solved fields. Related apparatus, systems, techniques and articles are also described.

Abstract: A method for preparing a modular planar interconnect plate includes steps of a) providing a metal blank sheet having a main region and two first lateral regions, b) forming two openings respectively in the first lateral regions, and c) stamping to form protrusions and depressions at the main region on lower and upper surfaces of the metal blank sheet. In the stamping step, each of two lower surrounding protrusions and two upper surrounding depressions is formed to surround a corresponding one of the openings, and each of an upper surrounding protrusion and a lower surrounding depression is formed to surround the first lateral regions and the corresponding ones of the protrusions and depressions formed at the main region.

Abstract: A test circuit for testing an integrated circuit includes a plurality of normal flip flops and a modified flip flop, wherein the integrated circuit includes a black box circuit and a plurality of combinational logic circuits. The normal flip flops each includes a first input pin, a second input pin and a first output pin and is configured to temporarily store the input value of the first input pin or the input value of the second input pin according to a scan enable signal. The modified flip flop includes a third input pin, a fourth input pin and a second output pin which are coupled to the black box circuit, the normal flip flops and the combinational logic circuits and is configured to temporarily store the input value of the third input pin or the input value of the fourth input pin according to a scan test mode signal.