Patents by Inventor Chuan-Ping Hou
Chuan-Ping Hou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369155Abstract: A semiconductor structure includes a semiconductor substrate, a metal gate structure disposed over the semiconductor substrate, an ILD structure over the semiconductor substrate and surrounding the metal gate structure, and a protecting layer over the ILD structure. A top surface of the protecting layer is aligned with a top surface of the metal gate structure. The protecting layer is separated from the metal gate structure.Type: ApplicationFiled: May 13, 2022Publication date: November 16, 2023Inventors: XIN ZHI WANG, CHUAN-PING HOU
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Patent number: 9607878Abstract: One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region.Type: GrantFiled: November 4, 2013Date of Patent: March 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming-Hui Chen, Chuan-Ping Hou, Chih-Ho Tai
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Publication number: 20150123239Abstract: One or more methods of forming shallow trench isolation (STI) and resulting semiconductor arraignments are provided. A method of forming STI includes forming a nitride liner in a first opening and second opening and recessing the nitride liner in the first opening and second opening while forming an oxide structure in the first opening and second opening, thus forming a first STI region in the first opening and a second STI region in the second opening. A semiconductor arraignment includes a first STI region in an active area and a second STI region in an isolation area, where a first recessed nitride layer height in the first STI region is different than a second recessed nitride layer height in the second STI region.Type: ApplicationFiled: November 4, 2013Publication date: May 7, 2015Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming-Hui Chen, Chuan-Ping Hou, Chih-Ho Tai
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Patent number: 7663185Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.Type: GrantFiled: May 27, 2006Date of Patent: February 16, 2010Assignee: Taiwan Semiconductor Manufacturing Co, LtdInventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
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Patent number: 7425486Abstract: A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the first trench dielectric and along inner surfaces of the trench. A second trench dielectric is deposited on the etch stop layer. The second trench dielectric and the etch stop layer are removed to expose the first trench dielectric in the trench. A conductive layer is formed on the first trench dielectric in the trench, such that the conductive layer, the first trench dielectric and the semiconductor substrate function as a trench capacitor.Type: GrantFiled: November 21, 2005Date of Patent: September 16, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chao-Chi Chen, Chuan-Ping Hou
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Patent number: 7332777Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: GrantFiled: September 7, 2005Date of Patent: February 19, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Publication number: 20070272954Abstract: A fin-FET device and a method for fabrication thereof both employ a bulk semiconductor substrate. A fin and an adjoining trough are formed within the bulk semiconductor substrate. The trough is partially backfilled with a deposited dielectric layer to form an exposed fin region and an unexposed fin region. A gate dielectric layer is formed upon the exposed fin region and a gate electrode is formed upon the gate dielectric layer. By employing a bulk semiconductor substrate the fin-FET device is fabricated cost effectively.Type: ApplicationFiled: May 27, 2006Publication date: November 29, 2007Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen, Di-Hong Lee
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Publication number: 20070117337Abstract: A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the first trench dielectric and along inner surfaces of the trench. A second trench dielectric is deposited on the etch stop layer. The second trench dielectric and the etch stop layer are removed to expose the first trench dielectric in the trench. A conductive layer is formed on the first trench dielectric in the trench, such that the conductive layer, the first trench dielectric and the semiconductor substrate function as a trench capacitor.Type: ApplicationFiled: November 21, 2005Publication date: May 24, 2007Inventors: Chao-Chi Chen, Chuan-Ping Hou
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Publication number: 20060237320Abstract: A method for forming a metal layer having a predetermined thickness on an underlying material is disclosed. According to the method, the underlying material is electroplated to form the metal layer having a fraction of the predetermined thickness thereon. The step of electroplating is interrupted for a predetermined period of time. The step of electroplating is then resumed to form the metal layer having the predetermined thickness on the underlying material, thereby improving planarity of the metal layer.Type: ApplicationFiled: April 25, 2005Publication date: October 26, 2006Inventors: K.Y. Lin, Chuan-Ping Hou, Keng-Hong Lin, Po-Jen Shih, S.K. Chen, Chao-Lung Chen, Chen Cheng Chou, Chyi Chern, De-Dui Liao
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Patent number: 7109117Abstract: A method for chemical mechanical polishing (CMP) of a shallow trench isolation (STI) structure employs a sequence of slurry polishes. In the first step the substrate is polished with either silica-based slurry or diluted ceria-based slurry. The first polishing is at a higher removal rate than the second polishing step. The polishing proceeds with some planarization but does not expose the polish stop layer. After partial planarization, the high selectivity slurry was used to complete the process. Improved throughput, lower defects and good within wafer uniformity are achieved.Type: GrantFiled: January 14, 2004Date of Patent: September 19, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Ching Tseng, Syun-Ming Jang, Li-Jia Yang, Chuan-Ping Hou
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Patent number: 7098116Abstract: A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.Type: GrantFiled: January 8, 2004Date of Patent: August 29, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Cheng Lu, Chuan-Ping Hou, Chu-Yun Fu, Chang Wen, Jang Syun Ming
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Patent number: 7026196Abstract: A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.Type: GrantFiled: November 24, 2003Date of Patent: April 11, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chuan-Ping Hou, Jhi-Cherng Lu, Kuang-Hsin Chen, Hsun-Chih Tsao
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Publication number: 20060012004Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: ApplicationFiled: September 7, 2005Publication date: January 19, 2006Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Patent number: 6955955Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: GrantFiled: December 29, 2003Date of Patent: October 18, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Patent number: 6930040Abstract: In a method of the present invention, an intermediate structure having a top surface is provided. An isolation trench is formed is the intermediate structure. Isolation material is deposited over the intermediate structure. The isolation material fills the isolation trench. Excess isolation material extends above the top surface of the intermediate structure. Part of the excess isolation material is removed until there is a predetermined thickness of isolation material remaining on the top surface of the intermediate structure. A contact opening is formed in the isolation material at the isolation trench. The contact opening extends through at least part of the intermediate structure. Contact material is deposited over the isolation material. The contact material fills the contact opening. Excess contact material, if any, that extends above the isolation material is removed. The excess isolation material is removed at least until the top surface of the intermediate structure is reached.Type: GrantFiled: October 22, 2003Date of Patent: August 16, 2005Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chuan-Ping Hou, Syun-Ming Jang, Ying-Ho Chen, Tung-Ching Tseng
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Publication number: 20050153555Abstract: A method for chemical mechanical polishing (CMP) of a shallow trench isolation (STI) structure employs a sequence of slurry polishes. In the first step the substrate is polished with either silica-based slurry or diluted ceria-based slurry. The first polishing is at a higher removal rate than the second polishing step. The polishing proceeds with some planarization but does not expose the polish stop layer. After partial planarization, the high selectivity slurry was used to complete the process. Improved throughput, lower defects and good within wafer uniformity are achieved.Type: ApplicationFiled: January 14, 2004Publication date: July 14, 2005Inventors: Tung-Ching Tseng, Syun-Ming Jang, Li-Jia Yang, Chuan-Ping Hou
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Publication number: 20050153519Abstract: A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.Type: ApplicationFiled: January 8, 2004Publication date: July 14, 2005Inventors: Chih-Cheng Lu, Chuan-Ping Hou, Chu-Yun Fu, Chang Wen, Jang Ming
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Publication number: 20050145937Abstract: In a method of manufacturing a semiconductor device, an initial structure is provided. The initial structure includes a substrate, a patterned silicon layer, and a covering layer. The substrate has a buried insulator layer formed thereon. The patterned silicon layer is formed on the buried insulator layer. The covering layer is formed on the patterned silicon layer. A first layer is formed on the initial structure. Part of the first layer is removed with an etching process, such that a sidewall portion of the patterned silicon layer is exposed and such that a remaining portion of the first layer remains at a corner where the patterned silicon layer interfaces with the buried insulator layer. An oxide liner is formed on the exposed sidewall portion. A recess may be formed in the buried insulator layer (prior to forming the first layer) and may extend partially beneath the patterned silicon layer.Type: ApplicationFiled: December 29, 2003Publication date: July 7, 2005Inventors: Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu
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Publication number: 20050110086Abstract: A method for forming a field effect transistor includes: forming a conductive region on an isolation layer formed on a substrate, and a cap dielectric layer on the conductive region; forming a sacrificial dielectric layer over the isolation layer and the cap dielectric layer, and on sidewalls of the conductive region; removing a portion of the sacrificial dielectric layer on the cap dielectric layer; removing the cap dielectric layer; removing remaining portions of the sacrificial dielectric layer; forming a gate on the conductive region; and forming source/drain (S/D) regions within the conductive region and adjacent to the gate. A field effect transistor includes a conductive region over an isolation layer formed on a substrate, the conductive region being substantially without undercut at the region within the isolation layer beneath the conductive region; a gate on the conductive region; and S/D regions within the conductive region and adjacent to the gate.Type: ApplicationFiled: November 24, 2003Publication date: May 26, 2005Inventors: Chuan-Ping Hou, Jhi-Cherng Lu, Kuang-Hsin Chen, Hsun-Chih Tsao
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Publication number: 20050090096Abstract: In a method of the present invention, an intermediate structure having a top surface is provided. An isolation trench is formed is the intermediate structure. Isolation material is deposited over the intermediate structure. The isolation material fills the isolation trench. Excess isolation material extends above the top surface of the intermediate structure. Part of the excess isolation material is removed until there is a predetermined thickness of isolation material remaining on the top surface of the intermediate structure. A contact opening is formed in the isolation material at the isolation trench. The contact opening extends through at least part of the intermediate structure. Contact material is deposited over the isolation material. The contact material fills the contact opening. Excess contact material, if any, that extends above the isolation material is removed. The excess isolation material is removed at least until the top surface of the intermediate structure is reached.Type: ApplicationFiled: October 22, 2003Publication date: April 28, 2005Inventors: Chuan-Ping Hou, Syun-Ming Jang, Ying-Ho Chen, Tung-Ching Tseng