Patents by Inventor Chuan-Shian FU

Chuan-Shian FU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12020998
    Abstract: A semiconductor structure includes a base layer, semiconductor dies on the base layer, and an inter-die connection layer electrically connecting two adjacent semiconductor dies. Each of the semiconductor dies includes an active area and a seal ring area including a seal ring surrounding the active area. The inter-die connection layer extends over adjacent portions of the seal rings in the seal ring areas of the two adjacent semiconductor dies.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: June 25, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chuan-Shian Fu, Cheng-Jyi Chang
  • Patent number: 11562960
    Abstract: A semiconductor device structure includes a gate structure, first epitaxial structures, a power rail, and a second epitaxial structure. The gate structure is disposed on a substrate extending in a first direction. The first epitaxial structures are surrounded by a contact structure disposed on opposite sides of the gate structure extending in the first direction. The power rail is spaced apart from the gate structure and the first epitaxial structures. The power rail extends in the second direction, which is perpendicular to the first direction. The second epitaxial structure is surrounded by the contact structure disposed directly beneath the power rail. The second epitaxial structure is electrically connected to the power rail.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: January 24, 2023
    Assignee: MediaTek Inc.
    Inventors: Chuan-Shian Fu, Shao-Hwang Sher
  • Publication number: 20220059461
    Abstract: A semiconductor device structure includes a gate structure, first epitaxial structures, a power rail, and a second epitaxial structure. The gate structure is disposed on a substrate extending in a first direction. The first epitaxial structures are surrounded by a contact structure disposed on opposite sides of the gate structure extending in the first direction. The power rail is spaced apart from the gate structure and the first epitaxial structures. The power rail extends in the second direction, which is perpendicular to the first direction. The second epitaxial structure is surrounded by the contact structure disposed directly beneath the power rail. The second epitaxial structure is electrically connected to the power rail.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Applicant: MediaTek Inc.
    Inventors: Chuan-Shian Fu, Shao-Hwang Sher
  • Patent number: 11195796
    Abstract: A semiconductor device structure includes a gate structure, first epitaxial structures, a power rail, and a second epitaxial structure. The gate structure is disposed on a substrate extending in a first direction. The first epitaxial structures are surrounded by a contact structure disposed on opposite sides of the gate structure extending in the first direction. The power rail is spaced apart from the gate structure and the first epitaxial structures. The power rail extends in the second direction, which is perpendicular to the first direction. The second epitaxial structure is surrounded by the contact structure disposed directly beneath the power rail. The second epitaxial structure is electrically connected to the power rail.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: December 7, 2021
    Assignee: MediaTek Inc.
    Inventors: Chuan-Shian Fu, Shao-Hwang Sher
  • Publication number: 20210320040
    Abstract: A semiconductor structure includes a base layer, semiconductor dies on the base layer, and an inter-die connection layer electrically connecting two adjacent semiconductor dies. Each of the semiconductor dies includes an active area and a seal ring area including a seal ring surrounding the active area. The inter-die connection layer extends over adjacent portions of the seal rings in the seal ring areas of the two adjacent semiconductor dies.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 14, 2021
    Inventors: Chuan-Shian FU, Cheng-Jyi CHANG
  • Patent number: 10644030
    Abstract: An integrated circuit includes a substrate and a plurality of standard cells. The standard cells are formed on the substrate, wherein each standard cell comprises a first fin, a second fin and a third fin, the second fin is located between the first fin and the third fin, and there is a first interval between the first fin and the second fin is different from a second interval between the first fin and the third fin.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 5, 2020
    Assignee: MEDIATEK INC.
    Inventors: Chuan-Shian Fu, Cheng-Jyi Chang, Shao-Hwang Sher
  • Publication number: 20190348367
    Abstract: A semiconductor device structure includes a gate structure, first epitaxial structures, a power rail, and a second epitaxial structure. The gate structure is disposed on a substrate extending in a first direction. The first epitaxial structures are surrounded by a contact structure disposed on opposite sides of the gate structure extending in the first direction. The power rail is spaced apart from the gate structure and the first epitaxial structures. The power rail extends in the second direction, which is perpendicular to the first direction. The second epitaxial structure is surrounded by the contact structure disposed directly beneath the power rail. The second epitaxial structure is electrically connected to the power rail.
    Type: Application
    Filed: April 15, 2019
    Publication date: November 14, 2019
    Applicant: MediaTek Inc.
    Inventors: Chuan-Shian Fu, Shao-Hwang Sher
  • Publication number: 20190123062
    Abstract: An integrated circuit includes a substrate and a plurality of standard cells. The standard cells are formed on the substrate, wherein each standard cell comprises a first fin, a second fin and a third fin, the second fin is located between the first fin and the third fin, and there is a first interval between the first fin and the second fin is different from a second interval between the first fin and the third fin.
    Type: Application
    Filed: July 30, 2018
    Publication date: April 25, 2019
    Inventors: Chuan-Shian FU, Cheng-Jyi CHANG, Shao-Hwang SHER