Abstract: Microcontroller units and methods for computing performance are provided. The disclosed microcontroller unit can include a central processing unit (CPU) configured to start a computing program, an accelerator comprising an in-memory computing (IMC) macro cluster configured to accelerate at least one layer of a machine learning model, a data memory (DMEM), and a direct memory access (DMA) module configured to transfer a weight data of a layer of a machine learning model from the DMEM to the IMC macro cluster.

Abstract: Various embodiments described herein provide for a digital In-Memory Computing (IMC) macro circuit that utilizes approximate arithmetic hardware to reduce the number of transistors and devices in the circuit relative to a convention digital IMC, thereby improving the area-efficiency of the digital IMC, but while retaining the benefits of reduced variability relative to an analog-mixed-signal (AMS) circuit. The proposed digital IMC macro circuit also includes custom full adder (FA) circuits with pass gate logic in a ripple carry adder (RCA) tree. The disclosed digital IMC macro circuit can also perform a vector-matrix dot product in one cycle while achieving high energy and area efficiency.