Patents by Inventor Chuan-Wei TSOU

Chuan-Wei TSOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220037518
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a gallium nitride (GaN) layer on a substrate; an aluminum gallium nitride (AlGaN) layer disposed on the GaN layer; a gate stack disposed on the AlGaN layer; a source feature and a drain feature disposed on the AlGaN layer and interposed by the gate stack; a dielectric material layer is disposed on the gate stack; and a field plate disposed on the dielectric material layer and electrically connected to the source feature, wherein the field plate includes a step-wise structure.
    Type: Application
    Filed: June 9, 2021
    Publication date: February 3, 2022
    Inventors: Wei Wang, Wei-Chen Yang, Yao-Chung Chang, Ru-Yi Su, Yen-Ku Lin, Chuan-Wei Tsou, Chun Lin Tsai
  • Patent number: 10446642
    Abstract: An epitaxial substrate and a method for forming the same are disclosed. The epitaxial substrate includes a substrate, a deposition layer, a buffer layer and an epitaxial layer. The deposition layer is directly formed on the substrate, wherein the deposition layer includes a gradient doping concentration, and has a first surface and a second surface which are opposite to each other; the gradient doping concentration has a minimum value at the first surface. The buffer layer is formed on the deposition layer, and an epitaxial layer is formed on the buffer layer. The epitaxial layer is mainly formed of group III-V nitride. The substrate and the deposition layer are formed of homogeneous material. Since the deposition layer is directly formed on the substrate, and the deposition layer and the substrate are formed of a homogeneous material, the epitaxial substrate includes a good heat dissipation efficiency and low leakage current.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALWAFERS CO., LTD.
    Inventors: Che-Ming Liu, Man-Hsuan Lin, Chih-Yuan Chuang, Shuo-Hung Hsu, Chuan-Wei Tsou, Wen-Ching Hsu
  • Publication number: 20180315815
    Abstract: An epitaxial substrate and a method for forming the same are disclosed. The epitaxial substrate includes a substrate, a deposition layer, a buffer layer and an epitaxial layer. The deposition layer is directly formed on the substrate, wherein the deposition layer includes a gradient doping concentration, and has a first surface and a second surface which are opposite to each other; the gradient doping concentration has a minimum value at the first surface. The buffer layer is formed on the deposition layer, and an epitaxial layer is formed on the buffer layer. The epitaxial layer is mainly formed of group III-V nitride. The substrate and the deposition layer are formed of homogeneous material. Since the deposition layer is directly formed on the substrate, and the deposition layer and the substrate are formed of a homogeneous material, the epitaxial substrate includes a good heat dissipation efficiency and low leakage current.
    Type: Application
    Filed: March 23, 2018
    Publication date: November 1, 2018
    Applicant: GLOBALWAFERS CO., LTD.
    Inventors: CHE-MING LIU, Man-Hsuan Lin, Chih-Yuan Chuang, Shuo-Hung Hsu, Chuan-Wei Tsou, Wen-Ching Hsu
  • Patent number: 10074533
    Abstract: This disclosure provides an epitaxial wafer, which includes: a silicon wafer having a central area and an extremity area enclosing the central area, the extremity area having a stepped profile; and an nitride epitaxial layer formed on the silicon wafer; wherein, the stepped profile has a width between 10 and 1500 ?m and a height between 1 and 500 ?m.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: September 11, 2018
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Po-Chun Yeh, Kan-Hsueh Tsai, Chuan-Wei Tsou, Heng-Yuan Lee, Hsueh-Hsing Liu, Han-Chieh Ho, Yi-Keng Fu
  • Patent number: 10014375
    Abstract: A III-nitride based semiconductor structure includes a substrate; a buffer layer disposed above the substrate; a first gallium nitrite (GaN) layer disposed above the buffer layer and including p-type GaN; a second GaN layer disposed on the first GaN layer and including at least a first region and a second region; a channel layer disposed above the second GaN layer; a barrier layer disposed above the channel layer; and a gate electrode disposed above the barrier layer. The first region of the second GaN layer is positioned correspondingly to the gate electrode and includes n-type GaN having a first doping concentration. The second region of the second GaN layer (such as the lateral portion of the second GaN layer) is positioned correspondingly to the areas outsides the gate electrode and includes n-type GaN having a second doping concentration larger than the first doping concentration.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: July 3, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Chuan-Wei Tsou, Po-Chun Yeh, Heng-Yuan Lee
  • Patent number: 9666685
    Abstract: A radio frequency (RF) power transistor includes a semiconductor heterostructure, a gate electrode, a drain electrode and a source electrode. The drain electrode includes an ohmic contact and a Schottky contact extending from the ohmic contact toward the gate electrode, spaced apart from the gate electrode (4) by a distance (LGD), and having a length (LEXT) being not less than 2 ?m and not greater than 4 ?m. A ratio of the length (LEXT) to a sum of the length (LEXT) and a distance (LGD) is greater than 0.83 and less than 0.98.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 30, 2017
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Shuo-Hung Hsu, Chuan-Wei Tsou, Yi-Wei Lien
  • Publication number: 20160218205
    Abstract: A radio frequency (RF) power transistor includes a semiconductor heterostructure, a gate electrode, a drain electrode and a source electrode. The drain electrode includes an ohmic contact and a Schottky contact extending from the ohmic contact toward the gate electrode, spaced apart from the gate electrode (4) by a distance (LGD), and having a length (LEXT) being not less than 2 ?m and not greater than 4 ?m. A ratio of the length (LEXT) to a sum of the length (LEXT) and a distance (LGD) is greater than 0.83 and less than 0.98.
    Type: Application
    Filed: April 1, 2016
    Publication date: July 28, 2016
    Applicant: National Tsing Hua University
    Inventors: Shuo-Hung HSU, Chuan-Wei TSOU, Yi-Wei LIEN
  • Publication number: 20160087090
    Abstract: A radio frequency (RF) power transistor includes: a semiconductor heterostructure that includes an undoped barrier layer and an active layer and that is formed with a continuous two dimensional electron gas (2DEG) channel having an ohmic source-aligned region, an ohmic drain-aligned region and a Schottky-aligned region; agate electrode; and source and drain electrodes. One of the source and drain electrodes includes an ohmic contact and a Schottky contact that extends from the ohmic contact toward the gate electrode. The 2DEG channel is normally on and extends continuously from the ohmic source-aligned region to the ohmic drain-aligned region. The Schottky contact overlaps and is capacitively coupled to the Schottky-aligned region of the 2DEG channel.
    Type: Application
    Filed: September 23, 2014
    Publication date: March 24, 2016
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Shuo-Hung HSU, Chuan-Wei TSOU, Yi-Wei LIEN