Patents by Inventor Chuan Wei WONG

Chuan Wei WONG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240353596
    Abstract: An illumination apparatus includes a micro lens array (MLA) including periodically arranged micro lenses. The apparatus also includes an array of periodically arranged first radiation-emitting elements disposed at a first distance from the MLA and configured to generate, in cooperation with the MLA, a structured light pattern. The apparatus includes a plurality of second radiation-emitting elements disposed at a second distance from the MLA and arranged to avoid matching any periodicity of the periodically arranged micro lenses and configured to generate, in cooperation with the MLA, a beam for flood illumination. The first distance is greater than the second distance.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 24, 2024
    Inventors: Lorenzo TONSA, Daniele PERENZONI, Francesco GARBELLI, Chuan Wei WONG, Alessandro PIOTTO
  • Publication number: 20150287681
    Abstract: Provided is a method of manufacturing a semiconductor package including a through wiring having precision and a low process defect. The method of manufacturing the semiconductor package includes preparing a conductive member; forming a plane part and projection parts projected from the plane part by removing portions of the conductive member; arranging the conductive member and a semiconductor chip, and forming a sealing member sealing the semiconductor chip and the conductive member; forming through wirings by exposing the projection parts of the conductive member from the sealing member; forming a re-wiring pattern layer which electrically connects the through wirings and the semiconductor chip; and forming external connection members which are electrically connected to the re-wiring pattern layer.
    Type: Application
    Filed: April 6, 2012
    Publication date: October 8, 2015
    Inventors: Say Hean Soh, Yuen Zien Siew, Chuan Wei Wong, Siew Boon Soh, Haoyang Chen
  • Publication number: 20080150107
    Abstract: A method for forming semiconductor packages is disclosed. The method involves providing a support substrate and forming at least one conductive layer thereon. The method also includes coupling the at least one conductive layer to a support face of a film substrate for securing the at least one conductive layer to the support face and removing the support substrate from the at least one conductive layer. The at least one interconnector is adhered to the film substrate for forming an interposer. The method further involves bonding a integrated circuit chip to the at least one conductive layer of the interposer and disposing a compound over the support face to thereby encapsulate the integrated circuit chip and the least one conductive layer for forming an encapsulated package therefrom. Portions of the at least one conductive layer is then exposed by removing the film substrate from the encapsulated package.
    Type: Application
    Filed: March 6, 2008
    Publication date: June 26, 2008
    Applicant: ADVANPACK SOLUTION PTES LTD
    Inventors: Teck Tiong TAN, Hwee Seng Jimmy CHEW, Kok Yeow Eddy LIM, Abd. Razak Bin CHICHIK, Kee Kwang LAU, Chuan Wei WONG