Abstract: Provided is a method for treating cancer by administering to a subject in need thereof with a pharmaceutical composition including a benzenesulfonamide derivative in combination with a cancer immunotherapeutic agent such as the immune check point inhibitor (ICI).

Abstract: A system and method, including software and hardware, for providing an accurate, real-time, and synchronized view of supply chain information. The system utilizes various RFID technologies (like an RFID tag, an RFID reader, and an RFID middleware software) to collect and manage data in real time. It then implements a synchronization mechanism to synchronize supply chain data from various data sources within and across a company in near real time fashion to allow different types of enterprise users, both internal and external, to access the synchronized information and take synchronized action within an appropriate timeframe.

Abstract: A system and method, including software and hardware, for providing an accurate, real-time, and synchronized view of supply chain information. The system utilizes various RFID technologies (like an RFID tag, an RFID reader, and an RFID middleware software) to collect and manage data in real time. It then implements a synchronization mechanism to synchronize supply chain data from various data sources within and across a company in near real time fashion to allow different types of enterprise users, both internal and external, to access the synchronized information and take synchronized action within an appropriate timeframe.

Abstract: In a memory device with a bank of N memory blocks, an address is generated for a first and a second one of the blocks. The first and second addresses include addresses for current first and second possible “refresh blocks”. If its memory block does not contend with the current first possible refresh block, an externally generated access to one of the N memory blocks is permitted and at least a portion of the refresh block is refreshed during a certain interval. In another aspect, the externally generated access is permitted and at least a portion of the current second possible refresh block is refreshed during the same certain interval if: i) the memory block of the externally generated access contends with the current first possible refresh block and ii) the current first and second possible refresh blocks are different ones of the N memory blocks.

Abstract: A method for integrating enterprise collaborative operations in the product lifecycle management (PLM) and a system thereof are proposed. The system comprises at least a message server, at least a web server, a system engineering service platform server, at least a PLM application system server and an enterprise portal server. The system can build a system integration environment between customers, central manufacturers, and providers and offer a collaborative platform between enterprises. Information can thus be interchanged in real time in this system integration environment in the whole PLM from idea through specification requirement, design, development, manufacturing to termination, thereby providing a system integration method and environment for collaborative management, development, manufacturing and marketing between enterprises, providers and customers.

Abstract: In a memory device with a bank of N memory blocks, an address is generated for a first and a second one of the blocks. The first and second addresses include addresses for current first and second possible “refresh blocks”. If its memory block does not contend with the current first possible refresh block, an externally generated access to one of the N memory blocks is permitted and at least a portion of the refresh block is refreshed during a certain interval. In another aspect, the externally generated access is permitted and at least a portion of the current second possible refresh block is refreshed during the same certain interval if: i) the memory block of the externally generated access contends with the current first possible refresh block and ii) the current first and second possible refresh blocks are different ones of the N memory blocks.

Abstract: A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks.

Abstract: A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks.

Abstract: A synchronous dynamic RAM capable of segmentally precharging each memory bank. In this SDRAM, each memory bank is divided into multiple memory blocks. Each of these memory blocks internally has its own row access circuitry, but performs independent precharging operation. Access to the memory bank can be cooperative externally, and precharge operation can be separately applied to these memory blocks while allowing utilization of row cache that is available on other blocks. The SDRAM further includes a control device for generating a dedicated precharge signal to each memory block according to a precharge signal for each memory bank. Each dedicated precharge signal independently precharges the corresponding memory block regardless of the access operations executed by other memory blocks.

Abstract: A low-current source circuit for generating a constant current and a reference voltage from a fluctuating voltage source is disclosed. A resistive circuit is electrically connected to the voltage source for determining amount of the constant current. A charging circuit is electrically connected to a second lead of the resistive circuit and the voltage source for supporting a charging path for the voltage source. A current output circuit is electrically connected to the second lead of the resistive circuit for outputting the constant current. A stabilizing circuit is electrically connected between the second lead of the resistive circuit and a control lead of the current output circuit for stabilizing the current output circuit. A reference voltage circuit is electrically connected to an output lead and the control lead of the current output circuit for generating the reference voltage.

Abstract: A self-biased voltage-regulated current source is disclosed. The present invention includes a current source circuit for generating a constant output current; a voltage source for supplying an unstable voltage for the current source circuit; a regulating circuit for generating a regulated voltage coupled to the current source circuit; and a bias circuit, coupled to the regulating circuit, for generating a bias current to the regulating circuit and the current source circuit, where the bias current is greater than the output current of the current source circuit.