Patents by Inventor ChuanChuan ZHU

ChuanChuan ZHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240323418
    Abstract: Disclosed are parallel encoding and decoding method and apparatus, a computer device, a storage medium, and a computer program product. The method includes: acquiring a synchronization node corresponding to a codec core, and transmitting a frame synchronization detection request to the synchronization node based on a frame to be encoded and decoded; acquiring a frame synchronization result corresponding to the frame synchronization detection request; and determining a encoding and decoding mode for the frame to be encoded and decoded based on the frame synchronization result, and encoding and decoding the frame to be encoded and decoded based on the encoding and decoding mode. By using the method, a plurality of codec cores can be employed to code and decode different frames in the same video in parallel, thereby improving the frame rate.
    Type: Application
    Filed: August 28, 2023
    Publication date: September 26, 2024
    Inventors: Chuanchuan ZHU, Shilin YAN, Jin SHAO, Cong JI
  • Patent number: 12008954
    Abstract: A method for compressing Demura compensation value including: acquiring original compensation values of a target panel; inputting the original compensation values into a spatial domain sampling model, performing a down-sampling to obtain spatial domain sampling values, inputting the original compensation values into a prediction mode overall model, and performing a numerical processing to obtain a plurality of mode characteristic values; performing a data reconstruction on the spatial sampling values and the plurality of mode characteristic values to obtain a reconstructed value set; performing a syntactic encoding on the spatial sampling values and the plurality of mode characteristic values to obtain a syntactic element code set; performing a mode selection according to the reconstructed value set and the syntactic element code set to obtain an optimal prediction mode; and acquiring and outputting a syntactic element code corresponding to the optimal prediction mode to obtain a Demura compensation value com
    Type: Grant
    Filed: March 29, 2023
    Date of Patent: June 11, 2024
    Assignee: GLENFLY TECH CO., LTD.
    Inventors: Ao Mei, Chuanchuan Zhu, Wei Wang
  • Publication number: 20240127749
    Abstract: A method for compressing Demura compensation value including: acquiring original compensation values of a target panel; inputting the original compensation values into a spatial domain sampling model, performing a down-sampling to obtain spatial domain sampling values, inputting the original compensation values into a prediction mode overall model, and performing a numerical processing to obtain a plurality of mode characteristic values; performing a data reconstruction on the spatial sampling values and the plurality of mode characteristic values to obtain a reconstructed value set; performing a syntactic encoding on the spatial sampling values and the plurality of mode characteristic values to obtain a syntactic element code set; performing a mode selection according to the reconstructed value set and the syntactic element code set to obtain an optimal prediction mode; and acquiring and outputting a syntactic element code corresponding to the optimal prediction mode to obtain a Demura compensation value com
    Type: Application
    Filed: March 29, 2023
    Publication date: April 18, 2024
    Inventors: Ao MEI, Chuanchuan ZHU, Wei WANG
  • Publication number: 20240129547
    Abstract: Disclosed is a method and a device for decompressing Demura compensation value based on random-access bit stream. The method includes reading a target compression code corresponding to a target pixel set according to a screen refresh instruction in response to the screen refresh instruction, and decoding the target compression code to obtain Demura compensation values.
    Type: Application
    Filed: March 24, 2023
    Publication date: April 18, 2024
    Inventors: Ao MEI, Chuanchuan ZHU, Wei WANG
  • Patent number: 10271049
    Abstract: Control methods of sample adaptive offset (SAO) filtering applied to an image processing system with an SAO filter are provided. The method includes the steps of: receiving video signal, wherein the video signal includes at least one group of picture (GOP) and the GOP has multiple frames, each having multiple coding tree units (CTUs); determining whether current frame is an intra-picture frame (I frame); turning on the SAO filter in response to determining that the current frame is the I frame to enable the SAO filter to perform an SAO filtering on the current frame and determining a CTU ratio of the CTUs being not performed with the SAO filtering for the current frame; and selectively turning off the SAO filter based on the CTU ratio, such that the SAO filter does not perform the SAO filtering on subsequent non-I frames in the GOP including the current frame.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 23, 2019
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Ao Mei, ChuanChuan Zhu
  • Publication number: 20190104307
    Abstract: Control methods of sample adaptive offset (SAO) filtering applied to an image processing system with an SAO filter are provided. The method includes the steps of: receiving video signal, wherein the video signal includes at least one group of picture (GOP) and the GOP has multiple frames, each having multiple coding tree units (CTUs); determining whether current frame is an intra-picture frame (I frame); turning on the SAO filter in response to determining that the current frame is the I frame to enable the SAO filter to perform an SAO filtering on the current frame and determining a CTU ratio of the CTUs being not performed with the SAO filtering for the current frame; and selectively turning off the SAO filter based on the CTU ratio, such that the SAO filter does not perform the SAO filtering on subsequent non-I frames in the GOP including the current frame.
    Type: Application
    Filed: November 27, 2017
    Publication date: April 4, 2019
    Inventors: Ao MEI, ChuanChuan ZHU
  • Patent number: 10212451
    Abstract: A method for RDO (Rate-Distortion Optimization) based on fit-curves contains at least the following steps: calculating a first fit-curve and a second fit-curve according to information regarding a first frame; carrying information regarding a second frame into the first and second fit-curves to calculate fit distortions and fit bit counts; calculating costs according to the fit distortions and the fit bit counts; determining the best block-division mode for the second frame according to the costs; and dividing the second frame into blocks according to the best block-division mode and encoding the second frame.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: February 19, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: ChuanChuan Zhu
  • Publication number: 20170324979
    Abstract: A method for RDO (Rate-Distortion Optimization) based on fit-curves contains at least the following steps: calculating a first fit-curve and a second fit-curve according to information regarding a first frame; carrying information regarding a second frame into the first and second fit-curves to calculate fit distortions and fit bit counts; calculating costs according to the fit distortions and the fit bit counts; determining the best block-division mode for the second frame according to the costs; and dividing the second frame into blocks according to the best block-division mode and encoding the second frame.
    Type: Application
    Filed: June 7, 2016
    Publication date: November 9, 2017
    Inventor: ChuanChuan ZHU
  • Patent number: 9686553
    Abstract: An advanced video coding and decoding chip and a method with an optimized processing sequence for the sub-blocks, each including 4×4 pixels, of a macroblock in a discrete cosine transform (DCT) and an inverse DCT are disclosed, wherein the compression hardware and the reconstruction hardware execute the compression and the reconstruction of at least part of a field in parallel.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 20, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: ChuanChuan Zhu, Jialiang Liu, Zixi Wang, Jin Shao
  • Patent number: 9654801
    Abstract: An advanced video coding and decoding chip and a method with a hardware design that calculates direct current coefficients in discrete-cosine-transformed residual blocks corresponding to sixteen sub-blocks within a macroblock and alternating current coefficients in the discrete-cosine-transformed residual blocks corresponding to the sixteen sub-blocks within the macroblock separately and in parallel.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 16, 2017
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventor: ChuanChuan Zhu
  • Publication number: 20160173876
    Abstract: An advanced video coding and decoding chip and a method with an optimized processing sequence for the sub-blocks, each including 4×4 pixels, of a macroblock in a discrete cosine transform (DCT) and an inverse DCT are disclosed, wherein the compression hardware and the reconstruction hardware execute the compression and the reconstruction of at least part of a field in parallel.
    Type: Application
    Filed: March 6, 2015
    Publication date: June 16, 2016
    Inventors: ChuanChuan ZHU, Jialiang LIU, Zixi WANG, Jin SHAO
  • Publication number: 20160173908
    Abstract: An advanced video coding and decoding chip and a method with a hardware design that calculates direct current coefficients in discrete-cosine-transformed residual blocks corresponding to sixteen sub-blocks within a macroblock and alternating current coefficients in the discrete-cosine-transformed residual blocks corresponding to the sixteen sub-blocks within the macroblock separately and in parallel.
    Type: Application
    Filed: April 17, 2015
    Publication date: June 16, 2016
    Inventor: ChuanChuan ZHU