Abstract: A manufacturing method of a semiconductor device includes the following steps. A III-V compound barrier layer is formed on a III-V compound semiconductor layer. A protection layer is formed on the III-V compound barrier layer. An opening is formed penetrating through the protection layer in a vertical direction and exposing a part of the III-V compound barrier layer. A p-type doped III-V compound material is formed in the opening. A patterned barrier layer is formed on the p-type doped III-V compound material. A contact area between the patterned barrier layer and the p-type doped III-V compound material is less than an area of a top surface of the p-type doped III-V compound material.

Abstract: An HEMT includes a first III-V compound layer, a second III-V compound layer, and a III-V compound cap layer. The second III-V compound layer is disposed on the first III-V compound layer. The III-V compound cap layer covers and contacts the second III-V compound layer. The composition of the III-V compound cap layer and the second III-V compound layer are different from each other. A first opening is disposed in the III-V compound cap layer. A first insulating layer includes two first insulating parts and two second insulating parts. The two first insulating parts cover a top surface of the III-V compound cap layer, and the two second insulating parts respectively contact two sidewalls of the first opening. A second opening is disposed between the two first insulating parts and between the two second insulating parts. A gate electrode is disposed in the second opening.

Abstract: A high electron mobility transistor (HEMT) device includes a substrate, a channel layer, a source, a drain, a buffer layer, and a plurality of amorphous regions. The channel layer is located above the substrate. The source is located on the channel layer. The drain is located on the channel layer. The buffer layer is located between the substrate and the channel layer. The plurality of amorphous regions are located in the buffer layer below the source and the drain.

Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

Abstract: Embodiments of this application disclose an object control method and device, a storage medium, and an electronic device. The method includes: detecting a first operation triggered in a client, the client displaying a virtual scene, and the first operation being used for instructing a target object in the virtual scene to move from one side of a target obstacle to the other side of the target obstacle; determining a target action to be performed by the target object, the target action being determined according to attributes of the target obstacle, and the target action being a crossing type or climbing type action performed by the target object to move from one side of the target obstacle to the other side of the target obstacle; and controlling, in the virtual scene, the target object to perform the target action. The embodiments of this application resolve a technical problem of an undiversified operation manner in an encounter of an obstacle in the related art.

Abstract: Embodiments of this application disclose an object control method performed by an electronic device. The method includes: detecting a first operation triggered in a client, the client displaying a virtual scene, and the first operation being used for instructing a target object in the virtual scene to move from one side of a target obstacle to the other side of the target obstacle; determining a target action to be performed by the target object, the target action being determined according to attributes of the target obstacle, and the target action being a crossing type or climbing type action performed by the target object to move from one side of the target obstacle to the other side of the target obstacle; and controlling, in the virtual scene, the target object to perform the target action.

Abstract: A semiconductor structure including a substrate, a dielectric layer, a first conductive layer, and a passivation layer is provided. The dielectric layer is disposed on the substrate. The first conductive layer is disposed on the dielectric layer. The passivation layer is disposed on the first conductive layer and the dielectric layer. The passivation layer includes a first upper surface and a second upper surface. The first upper surface is located above a top surface of the first conductive layer. The second upper surface is located on one side of the first conductive layer. A height of the first upper surface is higher than a height of the second upper surface. The height of the second upper surface is lower than or equal to a height of a lower surface of the first conductive layer located between a top surface of the dielectric layer and the first conductive layer.

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a gate dielectric layer on a substrate, forming a gate material layer on the gate dielectric layer, patterning the gate material layer and the gate dielectric layer to form a gate structure, removing a portion of the gate dielectric layer, forming a spacer adjacent to the gate structure and at the same time forming an air gap between the gate dielectric layer and the spacer, and then forming a source/drain region adjacent to two sides of the spacer.

Abstract: An electrically controlled nanomagnet and a spin orbit torque magnetic random access memory (SOT-MRAM) including the same are provided. The electrically controlled nanomagnet includes: a first spin-Hall material layer including a first spin-Hall material; a second spin-Hall material layer including a second spin-Hall material; and a first magnetic layer disposed between the first spin-Hall material layer and the second spin-Hall material layer, wherein the first spin-Hall material and the second spin-Hall material are substantially mirror image to each other.

Abstract: Embodiments of this application disclose an object control method and device, a storage medium, and an electronic device. The method includes: detecting a first operation triggered in a client, the client displaying a virtual scene, and the first operation being used for instructing a target object in the virtual scene to move from one side of a target obstacle to the other side of the target obstacle; determining a target action to be performed by the target object, the target action being determined according to attributes of the target obstacle, and the target action being a crossing type or climbing type action performed by the target object to move from one side of the target obstacle to the other side of the target obstacle; and controlling, in the virtual scene, the target object to perform the target action. The embodiments of this application resolve a technical problem of an undiversified operation manner in an encounter of an obstacle in the related art.

Abstract: An electrically controlled nanomagnet and a spin orbit torque magnetic random access memory (SOT-MRAM) including the same are provided. The electrically controlled nanomagnet includes: a first spin-Hall material layer including a first spin-Hall material; a second spin-Hall material layer including a second spin-Hall material; and a first magnetic layer disposed between the first spin-Hall material layer and the second spin-Hall material layer, wherein the first spin-Hall material and the second spin-Hall material are substantially mirror image to each other.

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.

Abstract: The present invention provides a method of making a tunneling effect transistor (TFET), the method includes: a substrate is provided, having a fin structure disposed thereon, the fin structure includes a first conductive type, a dielectric layer is then formed on the substrate and on the fin structure, a gate trench is formed in the dielectric layer, and a first work function metal layer is formed in the gate trench, the first work function metal layer defines at least a left portion, a right portion and a central portion, an etching process is performed to remove the central portion of the first work function metal layer, and to form a recess between the left portion and the right portion of the first work function metal layer, afterwards, a second work function metal layer is formed and filled in the recess.

Abstract: A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33.

Abstract: A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33.

Abstract: A method of manufacturing antenna by laser carving comprising the following steps: to attach metal material such as copper, silver etc. onto the base plate by a method of conductive coating by spraying; and then to trim the metal material to complete the shape of an antenna by laser carving. Thereby, the size and shape of the antenna are not limited, and the antenna can be manufactured on a non-planar base plate, thus the height of the entire antenna module can be reduced.