Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

Abstract: The present application discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate, a gate dielectric layer, a floating gate, a first dielectric layer and a control gate. The gate dielectric layer is disposed on the substrate. The floating gate is disposed on the gate dielectric layer and has at least one tip on a top surface of the floating gate. The first dielectric layer is disposed on the floating gate. The control gate is disposed above the first dielectric layer and at least partially overlaps the floating gate.

Abstract: A non-volatile memory cell includes a substrate, a first isolation structure positioned in a first region on the substrate, a second isolation structure surrounding a second region on the substrate, a control gate positioned on the first isolation structure in the first region, a first insulating layer positioned on the control gate, a second insulating layer positioned on the portion of the substrate in the second region, and a floating gate positioned on the first insulating layer and the second insulating layer.

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: A non-volatile memory cell includes a substrate, a first isolation structure positioned in a first region on the substrate, a second isolation structure surrounding a second region on the substrate, a control gate positioned on the first isolation structure in the first region, a first insulating layer positioned on the control gate, a second insulating layer positioned on the portion of the substrate in the second region, and a floating gate positioned on the first insulating layer and the second insulating layer.

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: A non-volatile memory cell includes a substrate, a first isolation structure positioned in a first region on the substrate, a second isolation structure surrounding a second region on the substrate, a control gate positioned on the first isolation structure in the first region, a first insulating layer positioned on the control gate, a second insulating layer positioned on the portion of the substrate in the second region, and a floating gate positioned on the first insulating layer and the second insulating layer.

Abstract: A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.

Abstract: A non-volatile memory cell includes a substrate, a first isolation structure positioned in a first region on the substrate, a second isolation structure surrounding a second region on the substrate, a control gate positioned on the first isolation structure in the first region, a first insulating layer positioned on the control gate, a second insulating layer positioned on the portion of the substrate in the second region, and a floating gate positioned on the first insulating layer and the second insulating layer.