Patents by Inventor Chuang-Ke Yeh
Chuang-Ke Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6538277Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.Type: GrantFiled: August 2, 2001Date of Patent: March 25, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hung-Cheng Sung, Di-Son Kuo, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin, Wen-Ting Chu
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Patent number: 6534821Abstract: A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell.Type: GrantFiled: August 10, 2001Date of Patent: March 18, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chuang-ke Yeh, Wen-Ting Chu, Di-Son Kuo
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Patent number: 6479859Abstract: A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage.Type: GrantFiled: February 6, 2001Date of Patent: November 12, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Tai-Fen Lin, Wen-Ting Chu, Chuang-Ke Yeh, Hung-Cheng Sung, Di-Son Kuo
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Publication number: 20020027241Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.Type: ApplicationFiled: August 2, 2001Publication date: March 7, 2002Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Hung-Cheng Sung, Di-Son Kuo, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin, Wen-Ting Chu
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Patent number: 6326660Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the float gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.Type: GrantFiled: March 13, 2000Date of Patent: December 4, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo
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Patent number: 6312989Abstract: A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell.Type: GrantFiled: January 21, 2000Date of Patent: November 6, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chuang-Ke Yeh, Wen-Ting Chu, Di-Son Kuo
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Patent number: 6309928Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F—N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.Type: GrantFiled: December 10, 1998Date of Patent: October 30, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hung-Cheng Sung, Di-Son Kuo, Chuang-Ke Yeh, Chia-Ta Hsieh, Yai-Fen Lin, Wen-Ting Chu
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Publication number: 20010022375Abstract: A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage.Type: ApplicationFiled: February 6, 2001Publication date: September 20, 2001Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Chia-Ta Hsieh, Tai-Fen Lin, Wen-Ting Chu, Chuang-Ke Yeh, Hung-Cheng Sung, Di-Son Kuo
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Patent number: 6229176Abstract: A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.Type: GrantFiled: February 25, 1999Date of Patent: May 8, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo
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Patent number: 6204126Abstract: A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage.Type: GrantFiled: February 18, 2000Date of Patent: March 20, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Tai-Fen Lin, Wen-Ting Chu, Chuang-Ke Yeh, Hung-Cheng Sung, Di-Son Kuo
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Patent number: 6171906Abstract: A method is provided for forming a split-gate flash memory cell having a sharp beak of poly which substantially improves the programming erase speed of the cell. The sharp beak is formed through an extra and judicious wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. The extra oxide dip causes the polyoxide to be removed peripherally thus forming a re-entrant cavity along the edge of the floating gate. The re-entrant beak is such that it does not get damaged during the subsequent process steps and is especially suited for cell sizes smaller than 0.35 micrometers.Type: GrantFiled: August 23, 1999Date of Patent: January 9, 2001Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chia-Ta Hsieh, Hung-Cheng Sung, Yai-Fen Lin, Chuang-Ke Yeh, Di-Son Kuo
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Patent number: 6046086Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split-gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the floating gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.Type: GrantFiled: June 19, 1998Date of Patent: April 4, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo
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Patent number: 5970371Abstract: A method is provided for forming a split-gate flash memory cell having a sharp beak of poly which substantially improves the programming erase speed of the cell. The sharp beak is formed through an extra and judicious wet etch of the polyoxide formed after the oxidation of the first polysilicon layer. The extra oxide dip causes the polyoxide to be removed peripherally thus forming a re-entrant cavity along the edge of the floating gate. The re-entrant beak is such that it does not get damaged during the subsequent process steps and is especially suited for cell sizes smaller than 0.35 micrometers.Type: GrantFiled: July 6, 1998Date of Patent: October 19, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ta Hsieh, Hung-Cheng Sung, Yai-Fen Lin, Chuang-Ke Yeh, Di-Son Kuo
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Patent number: 5879992Abstract: A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.Type: GrantFiled: July 15, 1998Date of Patent: March 9, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Ta Hsieh, Yai-Fen Lin, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo