Abstract: Disclosed approaches for multiplying a sparse matrix by dense a vector or matrix include first memory banks for storage of column indices, second memory banks for storage of row indices, and third memory banks for storage of non-zero values of a sparse matrix. A pairing circuit distributes an input stream of vector elements across first first-in-first-out (FIFO) buffers according to the buffered column indices. Multiplication circuitry multiplies vector elements output from the first FIFO buffers by corresponding ones of the non-zero values from the third memory banks, and stores products in second FIFO buffers. Row-aligner circuitry organize the products output from the second FIFO buffers into third FIFO buffers according to row indices in the second memory banks. Accumulation circuitry accumulates respective totals from products output from the third FIFO buffers.

Abstract: According to some embodiments, data to be exchanged via a system input output interface may be determined at a processor. It may then be arranged to exchange the data via a coherent input output device coupled to a coherent system interconnect. Other embodiments are described.

Abstract: According to some embodiments, data to be exchanged via a system input output interface may be determined at a processor. It may then be arranged to exchange the data via a coherent input output device coupled to a coherent system interconnect. Other embodiments are described.