Patents by Inventor Chuanjia WU

Chuanjia WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11456377
    Abstract: The semiconductor device includes: a substrate; a semiconductor layer disposed on one side of the substrate, the semiconductor layer including a channel layer and a barrier layer, and a two-dimensional electron gas being formed at an interface between the channel layer and the barrier layer; a source, a gate, and a drain disposed on one side of the semiconductor layer away from the substrate; and at least two drain junction terminals located on the side of the semiconductor layer away from the substrate and disposed at intervals between the gate and the drain, the at least two drain junction terminals being electrically connected to the drain respectively. In the embodiments of the present application, the on-resistance of the device can be reduced while the current collapse phenomenon is eliminated, thereby improving the long-term reliability of the device.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 27, 2022
    Assignee: GPOWER SEMICONDUCTOR INC.
    Inventor: Chuanjia Wu
  • Publication number: 20200259010
    Abstract: The semiconductor device includes: a substrate; a semiconductor layer disposed on one side of the substrate, the semiconductor layer including a channel layer and a barrier layer, and a two-dimensional electron gas being formed at an interface between the channel layer and the barrier layer; a source, a gate, and a drain disposed on one side of the semiconductor layer away from the substrate; and at least two drain junction terminals located on the side of the semiconductor layer away from the substrate and disposed at intervals between the gate and the drain, the at least two drain junction terminals being electrically connected to the drain respectively. In the embodiments of the present application, the on-resistance of the device can be reduced while the current collapse phenomenon is eliminated, thereby improving the long-term reliability of the device.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventor: Chuanjia Wu
  • Publication number: 20200058573
    Abstract: The present disclosure provides a heat dissipation structure of a semiconductor device and a semiconductor device, and it relates to a field of semiconductor technology. A heat dissipation structure of a semiconductor device according to an embodiment includes a first heat dissipation window formed on an upper surface of the heat dissipation structure at a side close to the semiconductor device, and at least one heat dissipation channel, the heat dissipation channel including an inflow channel and an outflow channel, transmitting a heat conducting medium to the first heat dissipation window via the inflow channel, the inflow channel including a first opening and a second opening, wherein the first opening is away from the first heat dissipation window, the second opening is close to the first heat dissipation window, and an opening area of the first opening is greater than an opening area of the second opening.
    Type: Application
    Filed: August 7, 2018
    Publication date: February 20, 2020
    Inventors: Chuanjia WU, Yi PEI
  • Patent number: 10103219
    Abstract: The present disclosure discloses a power semiconductor device and a method for manufacturing the same. The power semiconductor device comprises: a substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, a gate electrode, and a junction termination structure located on the barrier layer. The power semiconductor device extends in a first direction from an edge of a side of the gate electrode close to the drain electrode to the drain electrode, the junction termination structure at least comprises a first region close to the gate electrode and a second region away from the gate electrode and the thickness of the first region is greater than that of the second region in a second direction perpendicular to the barrier layer. The junction termination structure can effectively improve the distribution of an electric field of the barrier layer and hence increase the breakdown voltage of the device.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: October 16, 2018
    Assignee: Gpower Semiconductor, Inc.
    Inventors: Yi Pei, Yuan Li, Chuanjia Wu
  • Publication number: 20170207300
    Abstract: The present disclosure discloses a power semiconductor device and a method for manufacturing the same. The power semiconductor device comprises: a substrate, a channel layer, a barrier layer, a source electrode, a drain electrode, a gate electrode, and a junction termination structure located on the barrier layer. The power semiconductor device extends in a first direction from an edge of a side of the gate electrode close to the drain electrode to the drain electrode, the junction termination structure at least comprises a first region close to the gate electrode and a second region away from the gate electrode and the thickness of the first region is greater than that of the second region in a second direction perpendicular to the barrier layer. The junction termination structure can effectively improve the distribution of an electric field of the barrier layer and hence increase the breakdown voltage of the device.
    Type: Application
    Filed: March 29, 2017
    Publication date: July 20, 2017
    Inventors: Yi PEI, Yuan LI, Chuanjia WU