Patents by Inventor Chuanning Wang

Chuanning Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12205816
    Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20250019814
    Abstract: A method is provided for fabricating a cathode film layer of lithium ion batteries through atmospheric plasma spraying (APS) without using polymer adhesive. The ratio of active substance can approach 100%. A cathode film layer fabricated by APS is porous, where, with the coordination of a liquid electrolyte, electrolyte penetration paths are provided to significantly increase the area of reaction. Hence, the effective thickness of the film layer is relatively thick and the capacity of battery is increased. As an example, the thickness of a film layer of lithium cobalt oxide fabricated accordingly reaches more than 100 microns and its maximum electric capacity per unit area reaches 6 milliampere-hours per square centimeter (mAh/cm2).
    Type: Application
    Filed: October 1, 2024
    Publication date: January 16, 2025
    Inventors: Chun-Laing Chang, Chun-Huang Tsai, Chang-Shiang Yang, Cheng-Yun Fu, Min-Chuan Wang, Tien-Hsiang Hsueh
  • Publication number: 20250012616
    Abstract: A continuous liquid level sensing system utilizing projected capacitance includes: a liquid contact layer, which has at least one surface for contacting a liquid and separates the liquid to generate a space that is dry; and a projected capacitance unit being disposed in the space and having a first capacitance value that is preset, wherein the projected capacitance unit does not directly contact the liquid, and the projected capacitance unit contacts the liquid contact layer, wherein when the liquid contact layer changes a preset electric field of the projected capacitance unit after contacting the liquid, the first capacitance value is changed to a second capacitance value; and a control device calculating a liquid level height of the liquid according to a change between the first capacitance value and the second capacitance value.
    Type: Application
    Filed: July 3, 2024
    Publication date: January 9, 2025
    Inventors: JEN-CHUAN WANG, ZI-HUAN LUO, SHIH-MING WU
  • Publication number: 20250006320
    Abstract: A method and a device for acquiring character information in a picture, a non-transitory storage medium, a page processing method, and a knowledge graph construction method are disclosed. The method for acquiring character information in a picture includes: acquiring a picture and extracting at least one piece of character information in the picture; and checking-and-correcting the at least one piece of character information based on a knowledge graph.
    Type: Application
    Filed: September 13, 2024
    Publication date: January 2, 2025
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Nan LIU, Chuan WANG, Xinyu MIAO, Yiming LEI, Hong WANG
  • Publication number: 20250007624
    Abstract: A method of self-testing a transceiver integrated circuit substrate includes: providing a test signal to a transmission line that is communicatively coupled, or selectively communicatively coupled, to an input of a power amplifier of a first transceiver subcircuit of the transceiver integrated circuit substrate; providing the test signal from the transmission line to an LNA of an LNA of a second transceiver subcircuit of the transceiver integrated circuit substrate; and measuring the test signal before amplification by the LNA, or after amplification by the LNA, or both.
    Type: Application
    Filed: March 20, 2024
    Publication date: January 2, 2025
    Inventors: Yunfei FENG, Li LIU, Chuan WANG, Vahid DABBAGH REZAEI, Vinod PANIKKATH, Alaaeldien Mohamed Abdelrazek MEDRA, Anosh DAVIERWALLA, Xinmin YU, Muhammad HASSAN, Wu-Hsin CHEN, Sherif Hassan Kamel EMBABI
  • Publication number: 20250007480
    Abstract: Aspects include amplifiers with different units for improved performance. One amplifier has a first transistor with first gate is coupled to a control input, and a first drain is coupled to a first terminal of an output, a second transistor with a second gate is coupled to the control input, and a second drain is coupled to a second terminal of the output. The amplifier has a third transistor with a third drain coupled to the first transistor source, and a third gate is coupled to a first terminal of an input, and a fourth transistor with a fourth drain is coupled to the second transistor source, and a fourth source gate is coupled to a second terminal of the input, where the first transistor source is not connected to the second transistor drain via one or more transistors.
    Type: Application
    Filed: March 20, 2024
    Publication date: January 2, 2025
    Inventors: Chuan WANG, Li LIU, Vinod PANIKKATH, Wu-Hsin CHEN, Yunfei FENG, Anosh DAVIERWALLA, Muhammad HASSAN
  • Publication number: 20240429454
    Abstract: A solid-state lithium battery includes a solid electrolyte layer, a first electrode layer structure, a second electrode layer structure, a first collector layer and a second collector layer. The first electrode layer structure includes a first buffer electrolyte layer and a first microporous electrode layer. The first buffer electrolyte layer is located between the first microporous electrode layer and the first surface of the solid electrolyte layer. The first buffer electrolyte layer is embedded with the first surface of the solid electrolyte layer. The second electrode layer structure is disposed on the second surface of the solid electrolyte layer. The first microporous electrode layer is disposed between the first collector layer and first buffer electrolyte layer. The second electrode layer structure is disposed between the second collector layer and the second surface of the solid electrolyte layer.
    Type: Application
    Filed: August 15, 2023
    Publication date: December 26, 2024
    Inventors: TIEN-HSIANG HSUEH, SHANG-EN LIU, MIN-CHUAN WANG, TING-KUEI TSAI, YU-LIN YEH, YU-CHEN LI, BO-HSIEN WU
  • Publication number: 20240419464
    Abstract: Disability-related information of a user of a computing device can be acquired, the computing device can present a scene with user interface elements to the user. An accessibility requirement of the user can be identified based on the acquired disability-related information of the user. A processing routine can be determined from a plurality of processing routines stored in a routine library based on the accessibility requirement of the user. One or more of the user interface elements of the scene can be modified using the determined processing routine. The scene with the modified one or more of the user interface elements can be presented to the user through the computing device.
    Type: Application
    Filed: June 19, 2023
    Publication date: December 19, 2024
    Inventors: Dong Chen, Ye Chuan Wang, Xiang Wei Li, Ju Ling Liu, Yu An, Wei Yan, Ting Ting Zhan
  • Publication number: 20240395536
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chia-Yang Hung, Huan-Just Lin, Sheng-Liang Pan, Yungtzu Chen, Po-Chuan Wang, Guan-Xuan Chen
  • Publication number: 20240393624
    Abstract: Structures for a thermo-optic phase shifter and methods of forming a thermo-optic phase shifter. The structure comprises an interconnect structure including a dielectric layer, a waveguide core on the dielectric layer, and a heater on the dielectric layer. The heater includes a resistive heating element positioned adjacent to the waveguide core.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 28, 2024
    Inventors: Brian McGowan, Ping-Chuan Wang, Michal Rakowski, Sujith Chandran, Yusheng Bian
  • Patent number: 12152135
    Abstract: Provided herein are monolayer films, and also multilayer films comprising a core, a subskin disposed on the core, and a skin disposed on the subskin. The films may have an Elmendorf tear in MD greater than about 7.0 g/?m, a dart impact greater than about 6.0 g/?m, and a 1% secant modulus greater than about 200 MPa. In multilayer films, the core comprises a first polyethylene blend comprising an ethylene 1-hexene copolymer and a high density polyethylene composition in an amount between about 0 wt. % and about 40 wt. %. Further provided herein are bags and laminates comprising the present films.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: November 26, 2024
    Assignee: ExxonMobil Chemical Patents Inc.
    Inventors: Marianne F. M. Smits, Ying Zou, Etienne R. H. Lernoux, Zhen-Yu Zhu, Xiao-Chuan Wang, Achiel J. M. Van Loon, Maria Josefina Carbone
  • Patent number: 12154784
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first opening through a dielectric layer, the first opening exposing a conductive region. A wet cleaning is used after the forming the first opening, and the first opening is treated after the wet cleaning the first opening, the treating the first opening comprising turning a sidewall treatment precursor and a bottom treatment precursor into a first plasma mixture, the sidewall treatment precursor being different from the bottom treatment precursor. The first opening is filled with a conductive material after the treating the first opening.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: November 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yang Hung, Huan-Just Lin, Sheng-Liang Pan, Yungtzu Chen, Po-Chuan Wang, Guan-Xuan Chen
  • Publication number: 20240387517
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a gate electrode, a gate electrode contact layer over the gate electrode, forming a dielectric layer over the gate electrode contact layer, and performing an etch through the dielectric layer, the etch forming an opening that exposes the gate electrode contact layer. The method further includes performing a post-etch treatment on the opening formed by the etch process by exposing the opening to a plasma. The method further includes forming gate electrode contacts in the openings after the post-etch treatment by a bottom-up deposition process.
    Type: Application
    Filed: July 28, 2024
    Publication date: November 21, 2024
    Inventors: Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan, Huan-Just Lin
  • Publication number: 20240387646
    Abstract: A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material. By reducing segregation of the material, overlying conductive material can be deposited on a smoother interface. By depositing on smoother interfaces, overall losses of the deposited material may be avoided, which improves the overall yield.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Inventors: Po-Chuan Wang, Chia-Yang Hung, Sheng-Liang Pan
  • Publication number: 20240387698
    Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a silicon oxycarbonitride spacer, a silicon oxycarbide spacer, a silicon nitride spacer, and a source/drain structure. The gate structure is on the semiconductor substrate. The silicon oxycarbonitride spacer is on a sidewall of the gate structure. The silicon oxycarbide spacer is on a sidewall of the silicon oxycarbonitride spacer. The silicon nitride spacer is on a sidewall of the silicon oxycarbide spacer, in which an upper portion of the silicon nitride spacer has a lower density than a lower portion of the silicon nitride spacer. The source/drain structure is on the semiconductor substrate and adjacent to the gate structure.
    Type: Application
    Filed: July 29, 2024
    Publication date: November 21, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sheng-Liang PAN, Yung-Tzu CHEN, Chung-Chieh LEE, Yung-Chang HSU, Chia-Yang HUNG, Po-Chuan WANG, Guan-Xuan CHEN, Huan-Just LIN
  • Patent number: 12147074
    Abstract: Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide structure including a waveguide core. The structure further comprises a silicide layer, a first dielectric layer arranged in a lateral direction between the silicide layer and the waveguide core, and a second dielectric layer positioned over the waveguide core, the silicide layer, and the first dielectric layer. The first dielectric layer comprises a first material having a first thermal conductivity, and the second dielectric layer comprises a second material having a second thermal conductivity that is less than the first thermal conductivity.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: November 19, 2024
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Brian McGowan, Ping-Chuan Wang, Oscar Restrepo
  • Publication number: 20240379302
    Abstract: In some implementations, a key structure may include a lower shell fixedly connected to a keyboard base. In addition, the device may include an upper shell assembled above the lower shell, where the upper shell is made of transparent plastic material, the upper shell is provided with having a through opening. The device may include a plurality of light guide columns extending downwardly from two sides of the bottom of the upper shell, where the plurality of light guide columns and the plurality of light-emitting sources are arranged opposite to each other. Moreover, the device may include a pressing shaft movably disposed between the lower shell and the upper shell, where a top end of the pressing shaft penetrates through the opening. Also, the device may include a spring disposed and elastically supported between the lower shell and the pressing shaft.
    Type: Application
    Filed: May 4, 2022
    Publication date: November 14, 2024
    Applicant: Voyetra Turtle Beach, Inc.
    Inventors: Kristian ZIRR, Wei Chuan WANG
  • Publication number: 20240379344
    Abstract: A method of forming a semiconductor device includes: forming a first conductive feature in a first dielectric layer disposed over a substrate; forming a second dielectric layer over the first dielectric layer; etching the second dielectric layer using a patterned mask layer to form an opening in the second dielectric layer, where the opening exposes the first conductive feature; performing an ashing process to remove the patterned mask layer after the etching; wet cleaning the opening after the ashing process, where the wet cleaning enlarges a bottom portion of the opening; and filling the opening with a first electrically conductive material.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Po-Chuan Wang, Guan-Xuan Chen, Chia-Yang Hung, Sheng-Liang Pan, Huan-Just Lin
  • Patent number: D1056874
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: January 7, 2025
    Assignee: Shenzhen Grandsun Electronic Co., Ltd.
    Inventors: Jiugao Peng, Haiquan Wu, Chuan Wang, Ruiwen Shi, Zhijun Zhang, Chuanqi Zhang
  • Patent number: RE50271
    Abstract: A zoom lens arranged along an optical axis includes a first lens group and a second lens group. The second lens group has at least one aspheric lens. The first lens group moves toward an image side and the second lens group moves away from the image side along the optical axis during zooming. The first lens group is moved for focusing, and the second lens group is moved for zooming.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: January 14, 2025
    Assignee: Young Optics Inc.
    Inventors: Kuo-Chuan Wang, Bing-Ju Chiang, Pin-Hsuan Hsieh, Kai-Yun Chen, Yu-Hung Chou