Abstract: Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an intrinsic structure includes a semiconductor device having an active region in a conduction layer, an isolation region in the conduction layer, an insulating layer formed over at least a portion of the active region and over at least a portion of the isolation region, a via outside the active region, and a conductive interconnect. The isolation region extends around the semiconductor device in an area outside the active region. The via extends through the insulating layer and down to the isolation region in the conduction layer, and the conductive interconnect is formed directly on the isolation region in the conduction layer.

Abstract: Extrinsic structure that is formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. Extrinsic structure is described that can reduce gate leakage current in transistors by over four orders of magnitude.

Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Abstract: Thermally-sensitive structures and methods for sensing the temperature in a region of a FET during device operation are described. The region may be at or near a region of highest temperature achieved in the FET. Metal resistance thermometry (MRT) can be implemented with gate or source structures to evaluate the temperature of the FET.

Abstract: A method for fabricating a metal structure for a semiconductor device is disclosed. The method begins with providing a wafer with a current input contact and current output contact. Remaining steps include loading the wafer into a deposition apparatus, depositing a layer of metal onto a predefined metal region, removing the wafer from the deposition apparatus, and performing an ex-situ passivation process. If additional layers are to be deposited and passivated, the steps are repeated until a predetermined number of layers of metal are deposited onto the predefined metal region. The predefined metal region is a gate metal opening if the metal structure is a gate contact for a field effect transistor. The ex-situ passivation process is achievable through oxidation or nitridation of the wafer using either oxygen plasma or a nitrogen plasma, respectively. Alternately, oxidation is also achievable through exposing the wafer to air at an elevated temperature.

Abstract: A method for fabricating a metal structure for a semiconductor device is disclosed. The method begins with providing a wafer with a current input contact and current output contact. Remaining steps include loading the wafer into a deposition apparatus, depositing a layer of metal onto a predefined metal region, removing the wafer from the deposition apparatus, and performing an ex-situ passivation process. If additional layers are to be deposited and passivated, the steps are repeated until a predetermined number of layers of metal are deposited onto the predefined metal region. The predefined metal region is a gate metal opening if the metal structure is a gate contact for a field effect transistor. The ex-situ passivation process is achievable through oxidation or nitridation of the wafer using either oxygen plasma or a nitrogen plasma, respectively. Alternately, oxidation is also achievable through exposing the wafer to air at an elevated temperature.