Patents by Inventor Chuan-Yi Wang

Chuan-Yi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6727189
    Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: April 27, 2004
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chuan-Yi Wang, Tsai-Sen Lin, Chon-Shin Jou, Chi-Ping Chung
  • Patent number: 6677216
    Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.
    Type: Grant
    Filed: October 1, 2002
    Date of Patent: January 13, 2004
    Assignee: Mosel Vitelic, Inc.
    Inventors: Chun-Pey Cho, Tsai-Sen Lin, Chou-Shin Jou, Chuan-Yi Wang, Jen-Chieh Chang, Yi-Fu Chung, Huei-Ping Hsieh
  • Publication number: 20030068868
    Abstract: Embodiments of the present invention relate to a method of making an IC capacitor. In one embodiment, the method comprises providing a substrate, forming a polycide layer on the substrate, and forming an insulating amorphous silicon layer on the polycide layer. The insulating amorphous silicon layer serves as an anti-reflection layer. The method further comprises implanting n-type ions into the insulating amorphous silicon layer to transform the insulating amorphous silicon layer into a conductive amorphous silicon layer, and patterning the polycide layer and the conductive amorphous silicon layer to form a bottom electrode on the substrate. A dielectric layer is formed on the bottom electrode and the substrate, and a conductor layer is formed on the dielectric layer. The conductor layer is patterned to form a top electrode on the dielectric layer.
    Type: Application
    Filed: October 1, 2002
    Publication date: April 10, 2003
    Applicant: MOSEL VITELIC, INC.
    Inventors: Chun-Pey Cho, Tsai-Sen Lin, Chou-Shin Jou, Chuan-Yi Wang, Jen-Chieh Chang, Yi-Fu Chung, Huei-Ping Hsieh
  • Publication number: 20020137343
    Abstract: Embodiments of the present invention relate to implanting arsenic into a wafer to quickly detect if there is metal contamination, such as iron, aluminum, or manganese, on the wafer. In accordance with an aspect of the present invention, a method for detecting metal contamination of a silicon chip comprises implanting arsenic ions into the silicon chip, and etching the silicon chip with a chemical etching solution. The existence of any metal contamination is detected by observing occurrence of silicon pits on the silicon chip caused by reaction between the arsenic ions and the metal contamination and etching with the chemical etching solution.
    Type: Application
    Filed: March 26, 2002
    Publication date: September 26, 2002
    Applicant: MOSEL VITELIC, INC. A Taiwanese Corporation
    Inventors: Chuan-Yi Wang, Tsai-Sen Lin, Chon-Shin Jou, Chi-Ping Chung
  • Patent number: 6153849
    Abstract: An apparatus and a method for preventing etch rate drop after a machine idle time in a plasma etch chamber are disclosed. In the apparatus, an enclosure for enclosing a top plate in the plasma etch chamber is provided which is equipped with a heater in fluid communication with the enclosure. The top plate which includes a dielectric window and an inductive coil can be heated to a temperature between about 35.degree. C. and about 45.degree. C. during machine idle time to prevent etch rate drop after the chamber is restarted. The plasma etch chamber may be an inductively coupled RF plasma etcher. The heater may be constructed by a heater housing which is in fluid communication with the enclosure, at least one heating lamp in the housing, and a blower for delivering heated air into the enclosure cavity.
    Type: Grant
    Filed: January 29, 1999
    Date of Patent: November 28, 2000
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ken-Yuan Yung, Ming-Shue Yan, Tsar-Yi Chen, Wen-Bing Lin, Chuan-Yi Wang
  • Patent number: 6134850
    Abstract: A method for earthquake-proof mounting a semiconductor process machine on a removable floor (or a raised floor) in a semiconductor fabrication plant. In the method, a modified I-beam which has a horizontally extending upper flange is provided for mounting under a removable floor and attaching through the floor directly to a process machine situated on top of the floor. The process machine may be attached to the modified I-beam through an L-shaped bracket that is attached to the support frame of the process machine with the horizontal flange of the bracket attached to the modified I-beam through apertures in the removable floor. The present invention further comprises an earthquake-proof mounting fixture for mounting a process machine on a removable floor in a semiconductor fabrication plant.
    Type: Grant
    Filed: February 3, 1999
    Date of Patent: October 24, 2000
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Ming-Chu Hui, Bo-Han Hsieh, Chuan-Yi Wang, Yien-Yuan Yang