Abstract: A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.

Abstract: A method, system, and computer usable program product for multiple threshold voltage cell families (mVt families) based integrated circuit design are provided in the illustrative embodiments. The integrated circuit includes cells, and a cell includes an electronic component. A design process is initialized by using cells from the mVt families in the design. The cells from the mVt families are included in iterative manipulation of the design. The cells from the mVt families are further included in violation cleanup and subsequent steps of the design process. A version of the design is produced that is usable to implement the circuit with the cells from the mVt families.

Abstract: A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit.