Abstract: Embodiments of the present disclosure relate to systems and methods for updating a System on Chip (SOC) image without using direct memory access (DMA) programming. A target SOC monitors a target mailbox to determine reception of a data packet of an SOC image received from a host computer, wherein the SOC image includes a plurality of data packets. The target SOC reads the data packet from a buffer of the target SOC and writes a status message to a host mailbox of the target SOC, wherein the status message is indicative of a reception status of the data packet.

Abstract: Embodiments of the present disclosure relate to systems and methods for updating a System on Chip (SOC) image without using direct memory access (DMA) programming. A target SOC monitors a target mailbox to determine reception of a data packet of an SOC image received from a host computer, wherein the SOC image includes a plurality of data packets. The target SOC reads the data packet from a buffer of the target SOC and writes a status message to a host mailbox of the target SOC, wherein the status message is indicative of a reception status of the data packet.

Abstract: Modified flow keys holding compressed IPv6 addresses are stored in a flow table to improve memory utilization. The compressed IPv6 addresses are utilized to access a compression table holding the full IPv6 address, and full IPv6 address are substituted into the modified flow key to form an unmodified flow key.

Abstract: Modified flow keys holding compressed IPv6 addresses are stored in a flow table to improve memory utilization. The compressed IPv6 addresses are utilized to access a compression table holding the full IPv6 address, and full IPv6 address are substituted into the modified flow key to form an unmodified flow key.

Abstract: A method and apparatus for high speed signal path arbitration and transfer of a plurality of source signals to a destination signal path, is provided. An arbiter system includes an arbiter and a multiplexer. The multiplexer includes a plurality of n inputs each coupled to receive a source signal from one of a plurality of source signal paths and an output coupled to provide an output signal to the destination signal path. The multiplexer is controlled by a plurality of n select signal values received from the arbiter. The arbiter is coupled to receive a plurality of request signal values which prompt the arbiter to control the multiplexer to pass one of the source signals to the destination signal path. The multiplexer includes a plurality of n multiplexer signal paths each extending from one of n multiplexer inputs to the multiplexer output. Time characteristics of each of the n multiplexer signal paths are unequal.