Abstract: Techniques are provided for re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexor. At least one PID re-map table is employed having re-map values indexed by n possible PID values of transport packets associated with at one transport stream of the multiple transport streams. The n possible PID values is less than or equal to the number of PID values which can be handled by the single transport demultiplexor, and is less than all possible PID values of transport packets within the multiple transport streams. The PID values within at least one transport stream are compared with the n possible PID values of the PID re-map table, and when a match is found, the table is indexed using the matching entry and a re-map value is generated therefrom. The re-map value replaces the original PID value within the transport packet.

Abstract: A command list controller for controlling hardware based on an instruction received from a central processing unit (CPU) is provided. Specifically, the controller of the present invention retrieves hardware and controller commands from memory based on one or more instructions received from the CPU. All hardware commands will be forwarded to the hardware for execution, while all controller commands will be executed by the controller. Controller commands that the controller of the present invention is capable of executing include, among others, event wait commands and sublist execution commands.

Abstract: Method, system and computer products are provided for re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexor. The re-mapping and interleaving technique ensures unique identification of transport packets associated with multiple transport streams to be multiplexed onto a transport channel for demultiplexing by a single transport demultiplexor. At least one PID re-map table is employed having re-map values indexed by n possible PID values of transport packets associated with at one transport stream of the multiple transport streams. The n possible PID values is less than or equal to the number of PID values which can be handled by the single transport demultiplexor, and is less than all possible PID values of transport packets within the multiple transport streams.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: In a transport stream demultiplexor device receiving an input transport stream comprising a plurality of data packets and including a filter device for removing one or more predetermined packets to form a partial transport stream, a real-time data remultiplexing system and method comprising: a device for detecting presence of a gap in the partial transport stream where predetermined packets have been removed and generating a signal indicating the gap location; a device for directly retrieving packet data having new content from a memory storage device, and storing the retrieved packet data into a staging buffer device for queued storage prior to insertion into the partial transport stream; and, a multiplexor device responsive to the flag for pulling a queued data packet from the staging buffer device and inserting the pulled packet into the gap as the partial transport stream is being transported on a real-time basis.

Abstract: Copy protection is provided at a mass storage device provided in or connected to a decoder for receiving digital transmissions of audio and video program material by virtual scrambling of blocks of data. Non-sequential storage locations for blocks of data are defined in accordance with a key and the file allocation table is encrypted and stored. Thus blocks of data remain intact and need not be decrypted upon playback, reducing processing time, while the program is effectively protected from reassembly without decryption of the file allocation table. The key(s) may be maintained internally within the decoder and need not be shared, thus avoiding a need for user identification and/or authentication. Software for encryption, including keys may be downloaded to the decoder through the same transmission link used for transmission of data files that may be encrypted in response to control signals or flags transmitted with data files to be protected.

Abstract: A transport demultiplexor system and queue remultiplexing methodology includes: a packet buffer for receiving data packets belonging to an input transport stream, each packet having a corresponding identifier identifying a program to which the packet belongs; a data unloader device for pulling successive packets from the packet buffer for storage in a memory storage device, and writing the pulled packets into contiguous address locations in the memory; and, a remultiplexor mechanism for generating an address offset associated with a next data packet pulled from the packet buffer to be stored in memory and writing it to a new memory location that is offset from a memory location assigned to a previously pulled packet, the offset defining a memory gap in the memory storage device capable of being filled new data content.

Abstract: Two data streams derived from a transmitted data stream are remultiplexed with a coarser granularity for storage in data blocks which assure that corresponding portions of each of the two data streams are made available in the same data block. The data streams are buffered in queues from which sub-blocks are transferred as buffer sections having sizes corresponding to relative bit rates therein in the order the sub-blocks are filled, preferably using bytes to interrupt processing. Thus, the sub-blocks will be grouped into data blocks in accordance with the correspondence of the data streams such as the time correspondence of audio and video data. As applied to digital video data transmissions, a system time clock (STC) value is stored in a sub-block header and/or a data block header and, using a look-up table or other arrangement for estimating a storage location, a data block can be retrieved from storage in accordance with a target STC value.

Abstract: A command list controller for controlling hardware based on an instruction received from a central processing unit (CPU) is provided. Specifically, the controller of the present invention retrieves hardware and controller commands from memory based on one or more instructions received from the CPU. All hardware commands will be forwarded to the hardware for execution, while all controller commands will be executed by the controller. Controller commands that the controller of the present invention is capable of executing include, among others, event wait commands and sublist execution commands.

Abstract: Data corrupted or lost in transmission over a lossy digital transmission link is replaced and/or omitted from data presented in connection with storage to and read out from a mass storage device. Different procedures are used to conceal artifacts corresponding to errored data based upon valid data preceding and following the error in a data stream and a size of the error.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: A digital video decoder system, method and article of manufacture are provided having integrated scaling capabilities for presentation of video in full size or a predetermined reduced size, while at the same time allowing for reduced external memory requirements for frame buffer storage. The integrated system utilizes an existing decimation unit to scale the decoded stream of video data when the system is in scaled video mode. Display mode switch logic oversees switching between normal video mode and scaled video mode, wherein the switching occurs without perceptual degradation of a display of the decoded stream of video data. Scaled decoded video frames are buffered in a frame buffer which is partitioned depending upon whether the digital video decoding system is in normal video mode or scaled video mode. In scaled video mode, the frame buffer accommodates both full size I and P frames, as well as scaled I, P & B frames.

Abstract: In a transport stream demultiplexor device receiving an input transport stream comprising a plurality of data packets and including a filter device for removing one or more predetermined packets to form a partial transport stream, a real-time data remultiplexing system and method comprising: a device for detecting presence of a gap in the partial transport stream where predetermined packets have been removed and generating a signal indicating the gap location; a device for directly retrieving packet data having new content from a memory storage device, and storing the retrieved packet data into a staging buffer device for queued storage prior to insertion into the partial transport stream; and, a multiplexor device responsive to the flag for pulling a queued data packet from the staging buffer device and inserting the pulled packet into the gap as the partial transport stream is being transported on a real-time basis.

Abstract: A transport demultiplexor system and queue remultiplexing methodology includes: a packet buffer for receiving data packets belonging to an input transport stream, each packet having a corresponding identifier identifying a program to which the packet belongs; a data unloader device for pulling successive packets from the packet buffer for storage in a memory storage device, and writing the pulled packets into contiguous address locations in the memory; and, a remultiplexor mechanism for generating an address offset associated with a next data packet pulled from the packet buffer to be stored in memory and writing it to a new memory location that is offset from a memory location assigned to a previously pulled packet, the offset defining a memory gap in the memory storage device capable of being filled new data content.

Abstract: Method, system and computer products are provided for re-mapping and interleaving transport packets of multiple transport streams for processing by a single transport demultiplexor. The re-mapping and interleaving technique ensures unique identification of transport packets associated with multiple transport streams to be multiplexed onto a transport channel for demultiplexing by a single transport demultiplexor. At least one PID re-map table is employed having re-map values indexed by n possible PID values of transport packets associated with at one transport stream of the multiple transport streams. The n possible PID values is less than or equal to the number of PID values which can be handled by the single transport demultiplexor, and is less than all possible PID values of transport packets within the multiple transport streams.

Abstract: A memory interface for an integrated system is presented which allows simultaneous, transparent access to multiple external memories coupled thereto. The memory interface resides within a functional unit of the integrated system and includes multiple memory ports, at least one of which is coupled to dedicated memory and one port to shared memory. The dedicated memory comprises private memory for the functional unit, while the shared memory is common memory coupled to the functional unit and other functional units of the integrated system. The memory interface has a controller for forwarding memory fetch requests generated by requesting units within the functional unit to the proper memory port as determined at system initialization. A lookahead request generator is employed for generating speculative lookahead fetch requests within the memory interface using information on received memory fetch requests and known memory access patterns.

Abstract: A compression/decompression engine is disclosed for reducing memory requirements of a decode system by storing decoded video data in compressed form. The compression engine comprises parsing chrominance UV data into separate chrominance U data and chrominance V data, and transform logic implementing a Hadamard transformation of multiple bytes of decoded video data in parallel into frequency domain signals. Compression logic is coupled to the transform logic and performs, preferably, a 2:1 transformation of the frequency domain signals to produce compressed video signals for storage in memory. The transform logic and compression logic transform and compress multiple bytes of decoded video data in parallel within a single clock cycle of the decode system. Upon retrieval from memory, the compressed data is returned to original format by the decompression engine, which employs the same transform logic as used by the compression engine.

Abstract: An address generation engine is disclosed for a digital video decoder unit coupled to memory in a digital video decoder system wherein the memory accommodates multi-format and/or reduced video data storage. The address generation engine includes a processor and address generation hardware. The processor, coupled to access encoded data to be decoded by the digital video decoder unit, has microcode for deriving from the encoded data relative location information including a vertical component and a horizontal component. The address generation hardware includes a row address register and a column address register for receiving the vertical component and horizontal component, respectively, derived by the processor.

Abstract: A digital signal decoder system for receiving compressed encoded digitized video signals and transmitting decompressed decoded digital video signals includes a FIFO Data Buffer, a RAM having (1) a compressed, encoded Data Buffer and (2) a data portion for storing decompressed digital video buffer data. A Memory Management Unit is provided for managing the RAM.

Abstract: A pipelined parallel vector processor is disclosed. In order to increase the performance of the parallel vector processor, the present invention decreases the time required to process a pair of vectors stored in a pair of vector registers. The vector registers are subdivided into a plurality of smaller registers. A vector, stored in a vector register, comprises N elements; however, each of the smaller registers store M elements of the vector, where M is less than N. An element processor, functioning in a pipeline mode, is associated with each smaller register for processing the M elements of the vectors stored in the smaller register and generating results of the processing, the results being stored in one of the vector registers. The smaller registers of the vector registers, and their corresponding element processors, are structurally configured in a parallel fashion. The element processors and their associated smaller registers operate simultaneously.