Abstract: A circuit structure for implementing the lookup table of a network switching device is provided. With the circuit structure, the memory space of the lookup table could be fully utilized, and the time spent in searching the table is guaranteed to be within a specific time interval. The circuit structure divides the memory space of the lookup table into N blocks, each of which contains L records. The N blocks are directly connected to all search and comparison engines of the M network ports via separate buses respectively. An address generator continuously issues sequential address signals 0, 1, 2 . . . , L?1 to all blocks. Upon receiving an address signal, each block delivers its addressed record to all search and comparison engines via its own bus. A search and comparison engine therefore would compare all N×L records of the lookup table after the address generator has finished a full cycle of issuing L addresses.