Patents by Inventor Chueh-Yang Liu
Chueh-Yang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10651174Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.Type: GrantFiled: May 14, 2019Date of Patent: May 12, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 10505041Abstract: A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.Type: GrantFiled: March 26, 2017Date of Patent: December 10, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Wei Yu, Hsu Ting, Chueh-Yang Liu, Yu-Ren Wang, Kuang-Hsiu Chen
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Publication number: 20190279979Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.Type: ApplicationFiled: May 14, 2019Publication date: September 12, 2019Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 10340268Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.Type: GrantFiled: October 4, 2016Date of Patent: July 2, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 10312084Abstract: A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.Type: GrantFiled: February 22, 2017Date of Patent: June 4, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Kuang-Hsiu Chen, Yi-Liang Ye, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 10199485Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.Type: GrantFiled: January 18, 2017Date of Patent: February 5, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 10128366Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.Type: GrantFiled: February 6, 2018Date of Patent: November 13, 2018Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 10079143Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.Type: GrantFiled: June 29, 2017Date of Patent: September 18, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hsu Ting, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20180204939Abstract: A semiconductor device includes a substrate including a first semiconductor material, a gate structure formed on the substrate, and a source stressor and a drain stressor formed in the substrate respectively in a recess at two sides of the gate structure. The source stressor and the drain stressor respectively include at least a first quantum wire and at least a second quantum wire formed on the first quantum wire. The first quantum wire includes the first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. And the second quantum wire includes the second semiconductor material.Type: ApplicationFiled: January 18, 2017Publication date: July 19, 2018Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20180158943Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. The gate structure includes a gate dielectric layer formed over the semiconductor substrate, a gate electrode formed over the gate dielectric layer, and a spacer formed on side surfaces of the gate dielectric layer and the gate electrode. A laterally extending portion of the epitaxial structure extends laterally at an area below a top surface of the semiconductor substrate in a direction toward an area below the gate structure. A lateral end of the laterally extending portion is below the spacer.Type: ApplicationFiled: February 6, 2018Publication date: June 7, 2018Inventors: Yu-Ying Lin, Kuan Hsuan KU, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu LIN, Chun Yao YANG, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9966266Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.Type: GrantFiled: April 25, 2016Date of Patent: May 8, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Chun-Wei Yu, Kuang-Hsiu Chen, Yi-Liang Ye, Hsu Ting, Neng-Hui Yang
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Publication number: 20180122707Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.Type: ApplicationFiled: November 1, 2016Publication date: May 3, 2018Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Wen-Jiun Shen, Yu-Ren Wang
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Patent number: 9960084Abstract: The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS region and a PMOS region defined thereon, next, a gate structure is formed on the substrate within the NMOS region, and a disposal spacer is formed on two sides of the gate structure, afterwards, a mask layer is formed on the PMOS region to expose the NMOS region, next, a recess is formed on two sides of the gate structure spaced from the gate structure by the disposal spacer within the NMOS region, the disposal spacer is then removed after the recess is formed, and an epitaxial layer is formed into the recess.Type: GrantFiled: November 1, 2016Date of Patent: May 1, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Wen-Jiun Shen, Yu-Ren Wang
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Publication number: 20180096995Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.Type: ApplicationFiled: October 4, 2016Publication date: April 5, 2018Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 9929264Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: GrantFiled: June 20, 2017Date of Patent: March 27, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yu-Ying Lin, Kuan Hsuan Ku, I-Cheng Hu, Chueh-Yang Liu, Shui-Yen Lu, Yu Shu Lin, Chun Yao Yang, Yu-Ren Wang, Neng-Hui Yang
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Patent number: 9899520Abstract: A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.Type: GrantFiled: December 22, 2015Date of Patent: February 20, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Liang Ye, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
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Patent number: 9871113Abstract: A semiconductor process including the following steps is provided. An epitaxial layer is formed on a substrate. An oxide layer is formed on the epitaxial layer, wherein the oxide layer includes a chemical oxide layer, a high-temperature oxide (HTO) layer or a surface modification oxide layer. An ion implant process is performed to the epitaxial layer to form a doped region in the epitaxial layer. The oxide layer is removed by using a diluted hydrofluoric acid (DHF) solution after performing the ion implant process, wherein a volume ratio of water to a hydrofluoric acid (HF) in the DHF solution is 200:1 to 1000:1.Type: GrantFiled: March 8, 2016Date of Patent: January 16, 2018Assignee: United Microelectronics Corp.Inventors: Chun-Wei Yu, Kuang-Hsiu Chen, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20170365703Abstract: A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed partially within the semiconductor substrate. A vertically extending portion of the epitaxial structure extends vertically above a top surface of the semiconductor substrate in an area adjacent the gate structure. A laterally extending portion of the epitaxial structure extends laterally at an area below the top surface of the semiconductor substrate in a direction toward an area below the gate structure and beyond an area where the epitaxial structure extends vertically. The device further includes an interlayer dielectric layer between a side surface of the vertically extending portion of the epitaxial structure and a side surface of the gate structure. A top surface of the laterally extending portion of the epitaxial structure directly contacts the interlayer dielectric layer.Type: ApplicationFiled: June 20, 2017Publication date: December 21, 2017Inventors: Yu-Ying LIN, Kuan Hsuan KU, I-Cheng HU, Chueh-Yang LIU, Shui-Yen LU, Yu Shu LIN, Chun Yao YANG, Yu-Ren WANG, Neng-Hui YANG
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Publication number: 20170330742Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.Type: ApplicationFiled: June 29, 2017Publication date: November 16, 2017Inventors: Hsu Ting, Chun-Wei Yu, Chueh-Yang Liu, Yu-Ren Wang
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Publication number: 20170309485Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.Type: ApplicationFiled: April 25, 2016Publication date: October 26, 2017Inventors: Yu-Ying Lin, Chueh-Yang Liu, Yu-Ren Wang, Chun-Wei Yu, Kuang-Hsiu Chen, Yi-Liang Ye, Hsu Ting, Neng-Hui Yang