Abstract: Packaged semiconductor devices including heat-dissipating structures and methods of forming the same are disclosed. In an embodiment, a semiconductor package includes a semiconductor die including a substrate, a front-side interconnect structure on a front-side of the substrate, and a backside interconnect structure on a backside of the substrate opposite the front-side interconnect structure; a support die disposed on the front-side interconnect structure; a heat-dissipating structure on the support die, the heat-dissipating structure being thermally coupled to the semiconductor die and the support die; a redistribution structure on the backside interconnect structure opposite the substrate, the redistribution structure being electrically coupled to the semiconductor die; and an encapsulant on the redistribution structure and adjacent to side surfaces of the semiconductor die, the support die, and the heat-dissipating structure.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Abstract: A semiconductor package includes electric integrated circuit dies, photoelectric integrated circuit dies, and an inter-chip waveguide. The electric integrated circuit dies are laterally encapsulated by a first insulating encapsulant. The photoelectric integrated circuit dies are laterally encapsulated by a second insulating encapsulant. Each one of photoelectric integrated circuit dies includes an optical input/output terminal. The inter-chip waveguide is disposed over the second insulating encapsulant, wherein the photoelectric integrated circuit dies are optically communicated with each other through the inter-chip waveguide.

Abstract: In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

Abstract: A three-dimensional integrated circuit stack comprises a first integrated circuit structure, a second integrated circuit structure bonding to the first integrated circuit structure, and a redistribution structure. The first integrated circuit structure comprises a first semiconductor device, a first buffer structure, a first interconnect structure, a first conductive via, and a first through via. The first semiconductor device is located between the first buffer structure and the first interconnect structure. The first conductive via is extending through the first buffer structure and in contact with the first semiconductor device. The first through via is extending from the first buffer structure to the first interconnect structure. The redistribution structure is disposed on the first buffer structure, electrically connected to the first semiconductor device through the first conductive via, and electrically connected to the first interconnect structure through the first through via.

Abstract: A semiconductor package includes a die, a first thermal pattern and an interposer. The first thermal pattern is disposed aside the die. The interposer is bonded to the die and includes a substrate, a wiring structure between the substrate and the die and a second thermal pattern. The second thermal pattern is thermally coupled to the first thermal pattern.

Abstract: A method for forming an optical device structure is provided. The method includes disposing a first end portion of an optical fiber into a fiber array unit structure. The first end portion penetrates through the fiber array unit structure. The method includes bonding the first end portion of the optical fiber to a co-packaged optical device. The method includes bonding a fiber shield structure to the fiber array unit structure and the co-packaged optical device after the first end portion is bonded to the co-packaged optical device. The fiber shield structure surrounds the optical fiber.

Abstract: Systems, devices and methods of manufacturing a system on silicon wafer (SoSW) device and package are described herein. A plurality of functional dies is formed in a silicon wafer. Different sets of masks are used to form different types of the functional dies in the silicon wafer. A first redistribution structure is formed over the silicon wafer and provides local interconnects between adjacent dies of the same type and/or of different types. A second redistribution structure may be formed over the first redistribution layer and provides semi-global and/or global interconnects between non-adjacent dies of the same type and/or of different types. An optional backside redistribution structure may be formed over a second side of the silicon wafer opposite the first redistribution layer. The optional backside redistribution structure may provide backside interconnects between functional dies of different types.

Abstract: In an embodiment, a method includes forming a device layer over a first substrate; forming a first interconnect structure over a front-side of the device layer; attaching a second substrate to the first interconnect structure; forming a second interconnect structure over a back-side of the device layer, the second interconnect structure comprising back-side memory elements, wherein the back-side memory elements and a first plurality of active devices of the device layer provide a first memory array; and forming conductive connectors over the second interconnect structure.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a photonic die, an encapsulant and a wave guide structure. The photonic die includes: a substrate, having a wave guide pattern formed at front surface; and a dielectric layer, covering the front surface of the substrate, and having an opening overlapped with an end portion of the wave guide pattern. The encapsulant laterally encapsulates the photonic die. The wave guide structure lies on the encapsulant and the photonic die, and extends into the opening of the dielectric layer, to be optically coupled to the wave guide pattern.

Abstract: A semiconductor package includes a semiconductor substrate, a plurality of first dies, a plurality of thermal conductive patterns and an interposer. The first dies are bonded to the semiconductor substrate. The thermal conductive patterns are bonded to the semiconductor substrate. The interposer is bonded to the first dies, and the first dies and the thermal conductive patterns are disposed between the semiconductor substrate and the interposer.

Abstract: A method for forming a semiconductor package is provided. The method includes forming a first photonic routing structure over a substrate, disposing the first photonic routing structure over a redistribution structure, disposing a second photonic routing structure and an optical engine die on the redistribution structure and forming a molding structure between and separating the first photonic routing structure and the second photonic routing structure.

Abstract: A quantum memory device includes: a waveguide configured to spatially confine paths of photons therein; a memory cell that includes a micro-ring resonator (MRR), a frequency tuner, and a quantum memory material portion, wherein the MRR includes a first segment that is parallel to a segment of the waveguide, wherein the frequency tuner is configured to modulate a photon resonance frequency in the MRR by modifying an effective refractive index within, or around, a second segment of the MRR, and wherein the quantum memory material portion includes a quantum memory material having a ground state and an excitation state that stores photons therein and located within or on a third segment of the MRR; and a control circuit configured to modulate the photon resonance wavelength in the MRR during a first step of a photon capture operation to match a predefined wavelength, and to generate captured photons in the MRR.

Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate having a front-side surface and a back-side surface, and an electrical device formed over the front-side surface of a substrate. The package structure includes a dielectric layer formed below and in direct contact with the back-side surface of the substrate, and a first optical device formed in the dielectric layer. The package structure also includes a protective layer formed below or above the first optical device; and an electro-optic effect material layer formed in the protective layer.

Abstract: A package structure and a formation method are provided. The method includes forming electrical devices over a substrate and forming an interconnect structure over front sides of the electrical devices. The method also includes thinning the substrate and forming backside through vias connecting to backsides of the electrical devices. The method also includes attaching a waveguide layer over backsides of the electrical devices and forming conductive vias through the waveguide layer and electrically connected to the backside through vias.

Abstract: Embodiments provide regulated power routing through various inactive features of a device. In one embodiment, such inactive features include a through via wall which can be formed in an encapsulating material of a die stack. In another embodiment, such inactive features include a heat dissipation features formed over the die stack. In another embodiment, such inactive features include dummy via blocks attached adjacent a die cube. Yet other embodiments may combine the features of these embodiments without limitation.

Abstract: Semiconductor device includes light-emitting die and semiconductor package. Light emitting die includes substrate and first conductive pad. Substrate has emission region located at side surface. First conductive pad is located at bottom surface of substrate. Semiconductor package includes semiconductor-on-insulator substrate, interconnection structure, second conductive pad, and through semiconductor via. Semiconductor-on-insulator substrate has linear waveguide formed therein. Interconnection structure is disposed on semiconductor-on-insulator substrate. Edge coupler is embedded within interconnection structure and is connected to linear waveguide. Semiconductor-on-insulator substrate and interconnection structure include recess in which light-emitting die is disposed. Edge coupler is located close to sidewall of recess. Second conductive pad is located at bottom of recess. Through semiconductor via extends across semiconductor-on-insulator substrate to contact second conductive pad.

Abstract: A package structure is provided, and includes an interposer, a control unit, a plurality of computing units, a signal transmission layer, and an electric-optical material. The control unit is bonded to the interposer. The computing units are disposed around and connected to the control unit. The signal transmission layer is formed in the control unit and the computing units. The electric-optical material is formed in the control unit and the computing units, and the electric-optical material overlaps the signal transmission layer.

Abstract: A method of manufacturing an electronic apparatus is described. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.