Patents by Inventor Chuen-Huei Yang
Chuen-Huei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8225237Abstract: A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output.Type: GrantFiled: November 27, 2008Date of Patent: July 17, 2012Assignee: United Microelectronics Corp.Inventors: Te-Hung Wu, Sheng-Yuan Huang, Cheng-Te Wang, Chia-Wei Huang, Ping-I Hsieh, Po-I Lee, Chuen Huei Yang, Pei-Ru Tsai
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Patent number: 8166424Abstract: A method for constructing an optical proximity correction (OPC) model is described. A test pattern is provided, and the test pattern is then written on a mask. The pattern on the mask is measured to obtain a modified pattern. An OPC model is constructed according to the modified pattern.Type: GrantFiled: September 16, 2008Date of Patent: April 24, 2012Assignee: United Microelectronics Corp.Inventors: Te-Hung Wu, Chuen-Huei Yang
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Patent number: 8042069Abstract: A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output.Type: GrantFiled: August 7, 2008Date of Patent: October 18, 2011Assignee: United Microelectronics Corp.Inventors: Yu-Shiang Yang, Te-Hung Wu, Yung-Feng Cheng, Chuen Huei Yang, Hsiang-Yun Huang, Hui-Fang Kuo, Shih-Ming Kuo, Lun-Hung Chen
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Patent number: 7913196Abstract: A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns.Type: GrantFiled: May 23, 2007Date of Patent: March 22, 2011Assignee: United Microelectronics Corp.Inventors: Te-Hung Wu, Chia-Wei Huang, Chuen Huei Yang, Sheng-Yuan Huang, Pei-Ru Tsai, Chih-Hao Wu
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Publication number: 20100131914Abstract: A method to determine a process window is disclosed. First, a pattern data is provided. Second, a bias set is determined. Then, a resizing procedure is performed on the pattern data in accordance with the bias set to obtain a usable final resized pattern to be a target pattern of changed area. The final resized pattern is consistent with a minimum spacing rule, a contact to poly rule and a contact to metal rule. Accordingly, the target pattern is output.Type: ApplicationFiled: November 27, 2008Publication date: May 27, 2010Inventors: Te-Hung Wu, Sheng-Yuan Huang, Cheng-Te Wang, Chia-Wei Huang, Ping-I Hsieh, Po-I Lee, Chuen Huei Yang, Pei-Ru Tsai
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Patent number: 7687206Abstract: The invention provides a mask pattern. The mask pattern comprises at least a continuous pattern. Each of the continuous patterns has a first pattern, a second pattern and a set of assistance patterns. The assistant patterns are located between the first pattern to the second pattern. The first pattern, the assistant patterns and the second pattern together form a closed opening.Type: GrantFiled: March 8, 2007Date of Patent: March 30, 2010Assignee: United Microelectronics Corp.Inventors: Chuan-Hsien Fu, Chuen-Huei Yang, Chien-Li Kuo, Shu-Ru Wang, Yu-Lin Wang
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Publication number: 20100070944Abstract: A method for constructing an optical proximity correction (OPC) model is described. A test pattern is provided, and the test pattern is then written on a mask. The pattern on the mask is measured to obtain a modified pattern. An OPC model is constructed according to the modified pattern.Type: ApplicationFiled: September 16, 2008Publication date: March 18, 2010Applicant: UNITED MICROELECTRONICS CORP.Inventors: Te-Hung Wu, Chuen-Huei Yang
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Patent number: 7669153Abstract: A method for correcting a photomask pattern is provided. The correcting method performs a verification of a focus-exposure matrix (FEM) and an overlay variation on a layout area having contact holes or vias in a layout pattern so as to generate a hint information. The layout pattern of the photomask is corrected according to the hint information to prevent the contact holes or vias from being exposed in arrangement to corresponding metal layer, poly layer, or diffusion layer.Type: GrantFiled: April 30, 2007Date of Patent: February 23, 2010Assignee: United Microelectronics Corp.Inventors: Te-Hung Wu, Chuen-Huei Yang, Sheng-Yuan Huang, Chia-Wei Huang, Pei-Ru Tsai
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Patent number: 7664614Abstract: A method of inspecting defect of a mask is provided. In this method, a database for storing a plurality of virtual simulation models is created. The virtual simulation models are determined by a plurality of factors including an optical effect and a chemical effect during the transferring the pattern of a mask to the photoresist layer on a wafer. A mask defect image is acquired. A simulation contour of the mask defect image is generated from at least one virtual simulation model in the database. Next, the acceptability of the mask is determined.Type: GrantFiled: November 2, 2007Date of Patent: February 16, 2010Assignee: United Microelectronics Corp.Inventors: Te-Hung Wu, Shih-Ming Yen, Chih-Hao Wu, Chuen-Huei Yang
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Publication number: 20100036644Abstract: A method to selectively amend a layout pattern is disclosed. First, a layout pattern including at least a first group and a second group is provided, wherein each one of the first group and the second group respectively includes multiple members. Second, a simulation procedure and an amendment procedure are respectively performed on all the members of the first group and the second group to obtain an amended first group and an amended second group. Then, the amended first group and the amended second group are verified as being on target or not. Afterwards, the layout pattern including the on target amended first group and the on target amended second group is output.Type: ApplicationFiled: August 7, 2008Publication date: February 11, 2010Inventors: Yu-Shiang Yang, Te-Hung Wu, Yung-Feng Cheng, Chuen Huei Yang, Hsiang-Yun Huang, Hui-Fang Kuo, Shih-Ming Kuo, Lun-Hung Chen
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Publication number: 20090119045Abstract: A method of inspecting defect of a mask is provided. In this method, a database for storing a plurality of virtual simulation models is created. The virtual simulation models are determined by a plurality of factors including an optical effect and a chemical effect during the transferring the pattern of a mask to the photoresist layer on a wafer. A mask defect image is acquired. A simulation contour of the mask defect image is generated from at least one virtual simulation model in the database. Next, the acceptability of the mask is determined.Type: ApplicationFiled: November 2, 2007Publication date: May 7, 2009Applicant: UNITED MICROELECTRONICS CORP.Inventors: Te-Hung Wu, Shih-Ming Yen, Chih-Hao Wu, Chuen-Huei Yang
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Publication number: 20080295062Abstract: A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns.Type: ApplicationFiled: May 23, 2007Publication date: November 27, 2008Inventors: Te-Hung Wu, Chia-Wei Huang, Chuen Huei Yang, Sheng-Yuan Huang, Pei-Ru Tsai, Chih-Hao Wu
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Publication number: 20080270969Abstract: A method for correcting a photomask pattern is provided. The correcting method performs a verification of a focus-exposure matrix (FEM) and an overlay variation on a layout area having contact holes or vias in a layout pattern so as to generate a hint information. The layout pattern of the photomask is corrected according to the hint information to prevent the contact holes or vias from being exposed in arrangement to corresponding metal layer, poly layer, or diffusion layer.Type: ApplicationFiled: April 30, 2007Publication date: October 30, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Te-Hung Wu, Chuen-Huei Yang, Sheng-Yuan Huang, Chia-Wei Huang, Pei-Ru Tsai
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Publication number: 20080220341Abstract: The invention provides a mask pattern. The mask pattern comprises at least a continuous pattern. Each of the continuous patterns has a first pattern, a second pattern and a set of assistance patterns. The assistant patterns are located between the first pattern to the second pattern. The first pattern, the assistant patterns and the second pattern together form a closed opening.Type: ApplicationFiled: March 8, 2007Publication date: September 11, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Hsien Fu, Chuen-Huei Yang, Chien-Li Kuo, Shu-Ru Wang, Yu-Lin Wang
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Publication number: 20080178140Abstract: A method for correcting a photomask pattern is disclosed. The correction method determines a layout condition according to the space and line width of a layout pattern. The layout condition is used to determine the type of optical proximity correction to be used for a layout pattern in order to generate a correction pattern, and the correction pattern is compared with a predetermined specification. Furthermore, a modified-rule optical proximity correction table is employed to correct the special layout pattern. Therefore, the fidelity correction may be easily implemented.Type: ApplicationFiled: January 18, 2007Publication date: July 24, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ling-Chieh Lin, Chuen-Huei Yang, Chien-Fu Lee, I-Hsiung Huang
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Patent number: 7312020Abstract: A lithography method for forming a plurality of patterns in a photoresist layer. A phase shift mask including a plurality of transparent main features, a plurality of first phase shift transparent regions, and a plurality of second phase shift transparent regions is provided. Each transparent main feature is surrounded by the first phase shift transparent regions and the second phase shift transparent regions interlaced contiguously along a periphery of the transparent main feature. Each of the first phase shift transparent regions has a phase shift relative to each of the second phase shift transparent regions. An exposure process is performed to irradiate the phase shift mask with light so that the patterns corresponding to the transparent main features are formed in the photoresist layer.Type: GrantFiled: November 10, 2003Date of Patent: December 25, 2007Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Chuen Huei Yang, Ming-Jui Chen, Venson Lee
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Patent number: 7141337Abstract: A phase shift mask includes a transparent substrate, a semi-dense pattern, and a dense pattern. The semi-dense pattern is formed on the transparent substrate including a plurality of phase shift regions and non-phase shift regions arranged successively. The dense pattern is formed on the transparent substrate including a plurality of non-phase shift regions, phase shift regions, and non-transparent regions.Type: GrantFiled: April 3, 2003Date of Patent: November 28, 2006Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Chuen-Huei Yang, Ming-Jui Chen, Wen-Tien Hung
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Patent number: 7008732Abstract: A photomask pattern on a substrate is provided. The photomask pattern comprises a main pattern and a sub-resolution assistant feature. The sub-resolution assistant feature is located on the sides of the main pattern. Furthermore, the sub-resolution assistant feature comprises a first assistant feature and a second assistant feature. The first assistant feature is formed close to the main pattern and the second assistant feature is formed further away from the main pattern but adjacent to the first assistant feature. There is a phase difference of 180° between the first assistant feature and the main pattern. Similarly, there is a phase difference of 180° between the second assistant feature and the first assistant feature. Since the main pattern is bordered by reverse-phase assistant feature, exposure resolution of the photomask is increased.Type: GrantFiled: June 9, 2003Date of Patent: March 7, 2006Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Chuen-Huei Yang, Wen-Tien Hung
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Publication number: 20050112473Abstract: The present invention provides a photomask comprising a substrate and a plurality of shielding patterns. The substrate comprising a plurality of shielding regions and a plurality of transparent regions, while each transparent region is disposed between two adjacent shielding regions and has one depression. The depression and the shielding region share a same edge and a sidewall of the depression is aligned with a sidewall of the shielding pattern.Type: ApplicationFiled: November 24, 2003Publication date: May 26, 2005Inventors: Wen-Tien Hung, Chin-Lung Lin, Chuen-Huei Yang
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Publication number: 20050100829Abstract: A lithography method for forming a plurality of patterns in a photoresist layer. A phase shift mask including a plurality of transparent main features, a plurality of first phase shift transparent regions, and a plurality of second phase shift transparent regions is provided. Each transparent main feature is surrounded by the first phase shift transparent regions and the second phase shift transparent regions interlaced contiguously along a periphery of the transparent main feature. Each of the first phase shift transparent regions has a phase shift relative to each of the second phase shift transparent regions. An exposure process is performed to irradiate the phase shift mask with light so that the patterns corresponding to the transparent main features are formed in the photoresist layer.Type: ApplicationFiled: November 10, 2003Publication date: May 12, 2005Inventors: Chin-Lung Lin, Chuen Huei Yang, Ming-Jui Chen, Venson Lee