Patents by Inventor Chuen-Jye Lin
Chuen-Jye Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080099928Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: ApplicationFiled: October 31, 2007Publication date: May 1, 2008Applicant: MEGICA CORPORATIONInventors: Jin-Yuan Lee, Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Publication number: 20080088019Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.Type: ApplicationFiled: October 31, 2007Publication date: April 17, 2008Inventors: Mou-Shiung Lin, Ming-Ta Lei, Chuen-Jye Lin
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Patent number: 7355288Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: GrantFiled: May 2, 2005Date of Patent: April 8, 2008Assignee: Megica CorporationInventors: Jin Yuan Lee, Ming Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Publication number: 20080067677Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.Type: ApplicationFiled: October 31, 2007Publication date: March 20, 2008Inventors: Mou-Shiung Lin, Ming-Ta Lei, Chuen-Jye Lin
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Patent number: 7338890Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: GrantFiled: May 24, 2005Date of Patent: March 4, 2008Assignee: Megica CorporationInventors: Jin Yuan Lee, Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Patent number: 7105920Abstract: A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.Type: GrantFiled: November 12, 2004Date of Patent: September 12, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Yuan Su, Chen-Der Huang, Pei-Haw Tsao, Chuen-Jye Lin
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Publication number: 20060163714Abstract: A package structure and fabrication method thereof. The structure includes a substrate having a terminal, a chip overlying the substrate, the chip having an active surface, having a center region and periphery region, the periphery region having an electrode thereon, a patterned cover plate overlying the chip and exposing the electrode, a conductive material electrically connecting the electrode and terminal, and an encapsulant covering the terminal, conductive material, and electrode, but exposing the cover plate overlying the center region of the chip.Type: ApplicationFiled: January 7, 2005Publication date: July 27, 2006Inventors: Pei-Haw Tsao, Chender Huang, Chuen-Jye Lin
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Publication number: 20060163729Abstract: A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.Type: ApplicationFiled: March 27, 2006Publication date: July 27, 2006Inventors: Mou-Shiung Lin, Ming-Ta Lei, Chuen-Jye Lin
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Publication number: 20060103006Abstract: A substrate design to improve chip package reliability is provided. The chip package includes a substrate having a ceramic layer formed in a recess. A die is attached to the substrate on the ceramic layer. The substrate may be attached to a printed circuit board. The substrate may be fabricated by forming a recess in a substrate, such as a multi-layer substrate formed of organic dielectric materials. A ceramic layer is then affixed to the substrate in the recess. A die may be attached to the ceramic layer and the substrate may be attached to a printed circuit board.Type: ApplicationFiled: November 12, 2004Publication date: May 18, 2006Inventors: Chao-Yuan Su, Chen-Der Huang, Pei-Haw Tsao, Chuen-Jye Lin
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Publication number: 20060060980Abstract: Disclosed is a method of manufacturing a semiconductor package device. In one embodiment, the method includes providing a package substrate having a first coefficient of thermal expansion and at least one bonding pad on the substrate. The method also includes forming an integrated circuit chip having electrical devices, having at least one coupling structure for electrically coupling the chip to the at least one bonding pad, and having a second coefficient of thermal expansion different than the first coefficient of thermal expansion. The method further includes removing a portion of a thickness of the chip that is free of the electrical devices sufficient to allow the chip to distort substantially with the substrate during temperature changes despite the mismatch in their respective coefficients of thermal expansion. The method also includes bonding the chip to the substrate using the at least one coupling structure and the at least one bonding pad.Type: ApplicationFiled: September 22, 2004Publication date: March 23, 2006Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: PEI-HAW TSAO, Chuen-Jye LIN, Szu-Wei LU, Ching Chun LU, Chender HUANG, Mirng-Ji LII
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Publication number: 20050215043Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: ApplicationFiled: May 24, 2005Publication date: September 29, 2005Inventors: Jin Lee, Ming-Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Publication number: 20050189650Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: ApplicationFiled: May 2, 2005Publication date: September 1, 2005Inventors: Jin Lee, Ming Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Patent number: 6917119Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: GrantFiled: August 11, 2003Date of Patent: July 12, 2005Assignee: Megic CorporationInventors: Jin Yuan Lee, Ming Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Publication number: 20050070085Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.Type: ApplicationFiled: October 12, 2004Publication date: March 31, 2005Inventors: Ching-Cheng Huang, Chuen-Jye Lin, Ming-Ta Lei, Mou-Shiung Lin
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Patent number: 6815324Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.Type: GrantFiled: February 15, 2001Date of Patent: November 9, 2004Assignee: MEGIC CorporationInventors: Ching-Cheng Huang, Chuen-Jye Lin, Ming-Ta Lei, Mou-Shiung Lin
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Publication number: 20040032024Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad.Type: ApplicationFiled: August 11, 2003Publication date: February 19, 2004Applicant: MEGIC CORPORATIONInventors: Jin Yuan Lee, Ming Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Patent number: 6642136Abstract: A new method and chip scale package is provided. A point of electrical contact over a substrate is exposed through an opening created through overlying layers of passivation and polymer or elastomer, deposited over the substrate. A barrier/seed layer is deposited. A first photoresist mask exposes the barrier/seed layer where this layer overlies and is adjacent to the contact pad. The exposed surface of the barrier/seed layer is electroplated. The first photoresist mask is removed, a second photoresist mask is created to define the solder bump exposing a surface area of the barrier/seed layer not overlying the contact pad. The solder bump is created, the second photoresist mask is removed. The exposed barrier/seed layer is etched in accordance with the electroplating, reflow of the solder bump is optionally performed.Type: GrantFiled: September 17, 2001Date of Patent: November 4, 2003Assignee: Megic CorporationInventors: Jin Yuan Lee, Ming Ta Lei, Ching-Cheng Huang, Chuen-Jye Lin
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Publication number: 20030099907Abstract: A process of rectifying a wafer thickness includes the following steps. A wafer is first provided with an active side. Next, a lithography process is performed to form a photoresist at the active side and to pattern at least a opening therein. Subsequently, a welding material is formed in the openings. Afterward, an adhesive carrier is attached over the patterned photoresist. Next, rectification operation is performed to reduce the wafer thickness. Subsequently, the adhesive carrier is removed and then the patterned photoresist is removed.Type: ApplicationFiled: November 29, 2001Publication date: May 29, 2003Inventors: Ming-Ta Tei, Chuen-Jye Lin, Hei-Mei Chen
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Publication number: 20020111009Abstract: In accordance with the objectives of the invention a new method is provided for the creation of metal bumps over surfaces of I/O pads. Contact pads are provided over the surface of a layer of dielectric. The aluminum of the I/O pads, which have been used as I/O pads during wafer level semiconductor device testing, is completely or partially removed over a surface area that is smaller than the surface area of the contact pad using methods of metal dry etching or wet etching. The contact pad can be accessed either by interconnect metal created in a plane of the contact pad or by via that are provided through the layer of dielectric over which the contact pad has been deposited. The process can be further extended by the deposition, patterning and etching of a layer of polyimide over the layer of passivation that serves to protect the contact pad.Type: ApplicationFiled: February 15, 2001Publication date: August 15, 2002Applicant: MEGIC CorporationInventors: Ching-Cheng Huang, Chuen-Jye Lin, Ming-Ta Lei, Mou-Shiung Lin
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Patent number: 6075281Abstract: A lead frame equipped with modified lead fingers which have inclined tip portions for achieving an improved wire bond is provided. The inclined tip portions on the lead fingers can be formed in a stamping process with an angle on a top surface of the inclined tip portion measured at smaller than 30.degree. from a horizontal plane of the lead finger. It is preferred that the inclined angle should be between about 5.degree. and about 30.degree., and more preferred that the angle should be between about 5.degree. and about 20.degree.. A wedge bond formed on the inclined tip portion of a lead finger has improved thickness and thermal stress endurance. The thermal stress endurance may be improved by at least 20% and preferably by at least 50% when tested in a thermal cycling test between 150.degree. C. and -65.degree. C.Type: GrantFiled: March 30, 1999Date of Patent: June 13, 2000Assignee: Vanguard International Semiconductor CorporationInventors: Kuang-Ho Liao, Tsung-Chieh Chen, Chuen-Jye Lin